Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Shimpei Iijima

Tokuo Kure

Eiji Takeda

Takashi Hashimoto

Atsushi Hiraiwa

Takashi Nishida

Koichiro Ishibashi

Takashi Kobayashi

Toshihiko Tanaka

Norio Hasegawa

Katsutaka Kimura

Yoshinobu Nakagome

Digh Hisamoto

Toshiaki Yamanaka

Akihiro Shimizu

Shinichiro Kimura

Naotaka Hashimoto

Yoshifumi Kawamoto

Nobuyoshi Kobayashi

Toru Kaga

Kozo Mochiji

Yasuhiro Sugawara

Hiroaki Oizumi

Ryuichi Izawa

Mitsuo Nanba

Yasuo Igura

Akemi Hamada

There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Semiconductor memory device having static random access memory

A boron doped amorphous silicon film is formed by CVD under the conditions of a pressure lower than 1 atm and a temperature higher than 200.degree. C. and lower than 400.degree. C. by using at least one of disilane and trisilane, and diborane as source gases. Since the resultant amorphous silicon film can diffuse impurities at a lower temperature than in the case of the polycrystalline silicon film formed by the conventional method, a pn junction much shallower than in the prior art can be formed.

Method of manufacturing semiconductor device

The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

Semiconductor device having a low-resistivity planar wiring structure

An X-ray mask comprises an absorber pattern composed of a material capable of absorbing X-ray, a mask substrate for supporting the absorber pattern, composed of a material capable of transmitting X-ray, and a support frame for supporting the mask substrate, wherein the mask substrate is composed of a mask substrate material whose impurity content is suppressed to reduce positional distortions generated by X-ray radiation. Generation of positional distortions by X-ray exposure is inhibited and an arrangement of mask pattern can be ensured with a high precision.

X-ray mask and method for producing same

Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.

Transistor with overlapping gate/drain and two-layered gate structures

Growing community of inventors

Akishima, Japan

Shimpei Iijima