Kabushiki Kaisha Toshiba

Shimon Maeda

Shinichi Ito

Suigen Kyoh

Masahiro Miyairi

Takashi Sato

Soichi Inoue

Toshiya Kotani

Hirokazu Kato

Shigeki Nojima

Hideki Kanai

Sachiko Kobayashi

Kenji Konomi

Ayako Kawanishi

Ryuji Ogawa

Noriyuki Honda

Koujirou Ohyoshi

According to one embodiment, a method for generating mask data is configured to form a circuit pattern on a substrate using a directed self-assembly material. The method includes extracting a first region, setting a second region and setting a third region. The first region does not existing in the circuit pattern and existing in an initial pattern. The initial pattern includes a plurality of interconnect patterns extending in a first direction. The second region is formed by elongating the first region in a second direction intersecting the first direction. The second region straddles the first region in the second direction. The third region includes at least one of the second regions. The directed self-assembly material is disposed in the third region.

Method for generating mask data and method for manufacturing integrated circuit device

According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.

Pattern forming method

In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.

Method for forming pattern and method for manufacturing semiconductor device

A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.

Pattern layout creation method, program product, and semiconductor device manufacturing method

A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

Pattern data creating method, pattern data creating program, and semiconductor device manufacturing method

A database creation method relating to semiconductor ICs, the database registering function block cells constituting a design data of semiconductor IC and evaluation values corresponding to the function block cells such that the function block cells are associated with the evaluation values, for each of the semiconductor ICs, the creation method includes judging whether or not that function block cells constituting a design data of desired semiconductor IC include an unregistered function block cell which is not registered in the database, calculating an unregistered evaluation value corresponding to the unregistered function block cell when the function block cells constituting the design data of the desired semiconductor IC are judged to include the unregistered function block cell, and updating the database by registering the unregistered function block cell and the unregistered evaluation value such that the unregistered function block cell is associated with the unregistered evaluation value.

Database creation method, database device and design data evaluation method

A graph is created in which mask patterns adjacent to one another at a distance in which desired printing resolution cannot be obtained in a lithography process among mask patterns generated based on a pattern layout design drawing are set as nodes connected to one another by edges. An odd number loop formed by an odd number of nodes is selected from closed loops. When the selected odd number loop is not isolated, based on whether a closed loop group in which a plurality of closed loops including the odd number loop are connected includes an even number loop formed by an even number of nodes, rearrangement target nodes are selected from the odd number loop included in the closed loop group according to different selection references. The layout of patterns described in the pattern layout design drawing is rearranged corresponding to the selected rearrangement target nodes.

Pattern layout designing method, semiconductor device manufacturing method, and computer program product

A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.

Process-model generation method, computer program product, and pattern correction method

A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

Design Pattern correcting method, process proximity effect correcting method, and semiconductor device manufacturing method

A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

Method and program for pattern data generation using a modification guide

A pattern producing method includes specifying a first pattern and a second pattern obtained by modifying the first pattern, specifying a correction area based on the second pattern, in a part of an area including the first pattern and the second pattern, producing at least a part of the first pattern, which is included in the correction area, as a correction target pattern, producing a part of the first or second pattern, which is not included in the correction area, as a correction reference pattern, correcting the correction target pattern on the basis of the correction target pattern and the correction reference pattern, and producing a pattern based on the corrected correction target pattern and the second pattern.

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Tokyo, Japan

Shimon Maeda