Cisco Technology, Inc.

Shimon Listman

Doron Shoham

John Joseph Williams, Jr

John Andrew Fingerhut

John H W Bettink

Eliahu Shapiro

In one embodiment, individual or groups of heat generating data processing operations are rate-controlled such that a component, a set of components, a board or line card, and/or an entire apparatus or any portion thereof stays within a corresponding heat budget. One or more heat price tags are associated with these data processing operations which are used to determine whether or not a corresponding data processing operation can be currently performed within one or more corresponding heat budgets. If so, the data procession operation proceeds. If not, the data processing operation is delayed. Examples of such data processing operations include, but are not limited to, data retrieval from memory, data storage in memory, lookup operations in memory, lookup operations in a binary or ternary content-addressable memory, regular expression processing, cryptographic processing, or data manipulation.

Rate-controlling of heat generating data processing operations

In one embodiment, batch entries include multiple content-addressable memory (CAM) entries, and CAM entries are allowed to be shared among different batch entries. For example, two or more batch entries might have a common set of bits (e.g., representing an address, an address prefix, etc.). Rather than consuming bits of multiple CAM entries, a single CAM entry can be programmed with this common information. Other CAM entries associated with different batch entries are programmed with the distinguishing/different values. A batch lookup operation on a batch entry of two or more CAM entries requires multiple lookup operations on the CAM entries. One embodiment uses a batch mask vector to provide information to decode what CAM entries are shared among which batch entries during a series of lookup operations, which can be performed in one or both directions through the CAM entries.

Batch entries sharing individual content-addressable memory entries

Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is typically performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.

Distributed packet processing with ordered locks to maintain requisite packet orderings

Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.

Error protection for lookup operations in a content-addressable memory (CAM) entries is disclosed. Values extended to include error protection or error protection fields are stored in CAM entries and a lookup operation is performed on a similarly extended lookup word to determine whether or not an entry is matched, that is, if all or all but some predetermined number of bits match one of the extended entries. For example, one implementation includes multiple CAM entries and logic configured to perform a lookup operation in parallel on each of the CAM entries based on a lookup word to determine whether or not a hit results, where the hit is determined if an entry matches the lookup word in all or all but k bit positions, where n and k are integers, n&#x3e;k, and k&#x3e;0.

Error protection for lookup operations in content-addressable memory entries

Methods and apparatus are disclosed for reading from and writing to storage using acknowledged phases of sets of data. In one implementation, a phase indication is maintained. A first value of the phase indication is associated with a first plurality of memory requests, and a second value of the phase indication is associated with a second plurality of memory requests. The first and second pluralities of memory requests are forwarded to a memory control component. A first acknowledgement that the first plurality of memory requests have been manipulated is received, which allows a next set of data to be sent using the acknowledged phase. In one implementation, the plurality of memory requests include a write request. In one implementation, the plurality of memory requests include a read request.

Growing community of inventors

Tel Mond, Israel

Shimon Listman