International Business Machines Corporation

Shimon Ben-Yehuda

Timothy John Slegel

Anthony Saporito

Brian David Barrick

Gregory William Alexander

John David Jabusch

Ronny Morad

Shady Copty

Ophir Erez

Alex Goryachev

Eli Bokshtein

In a multi-core computer system, a method for dealing with a fault with a core includes detecting a fault in one of the cores. Information is transferred from a recovery buffer to a mapper. The information includes logical register mapping information. A recovery is performed using the information in the mapper. If a recovery cannot proceed, a sparing can be initiated using the information in the mapper.

Simplified processor sparing

A novel and useful stress test generation mechanism that is operative to divide the task of generating test case programs (files) into a first randomization stage and a second randomization stage. The first randomization stage selects the scenario and the second randomization stage generates a test case in accordance with the chosen scenario. In other words, during stage 1, a test scenario (i.e. value-categories) is randomly determined (using the weights assigned to the value-categories within each scenario-dimension). In stage 2, a test is randomly generated for the chosen scenario. Thus, for each scenario-dimension, one or more values are generated randomly for the chosen value-category. Once the values for the value-categories are generated, an output test file for use by the logic verification is generated.

High quality logic verification stress test generation using two-stage randomization

A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

System-level testcase generation

Growing community of inventors

Haifa, Israel

Shimon Ben-Yehuda