Arizona State University

Shimeng Yu

Jae-sun Seo

Sarma Vrudhula

Yu Cao

Niranjan Kulkarni

Jinghua Yang

Jieping Ye

Rui Liu

A multi-layer vector-matrix multiplication (VMM) apparatus is provided. The multi-layer VMM apparatus includes a three-dimensional (3D) NAND flash structure having multiple transistor array layers each includes a number of transistors configured to store a respective weight matrix and a number of word lines configured to receive respective selection voltages corresponding to a respective input vector. Accordingly, each of the transistor array layers can perform a respective VMM operation by multiplying the respective selection voltages with the respective weight matrix. Thus, by providing the respective selection voltages to each of the multiple transistor array layers in a sequential order, it may be possible to carry out a multi-layer VMM operation in the 3D NAND flash structure with reduced footprint, thus making it possible to support a deep neural network (DNN) via such advanced techniques as in-memory computing.

Multi-layer vector-matrix multiplication apparatus for a deep neural network

A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

Resistive random-access memory for embedded computation

Resistive random-access memory for exclusive NOR (XNOR) neural networks

A static random access memory (SRAM) bit cell and a related SRAM array are provided. In one aspect, an SRAM cell is configured to perform an XNOR function on a first input value and a second input value. In another aspect, a number of the SRAM cells can be employed to form an SRAM array for supporting deep neural network and machine learning applications. The SRAM cell is coupled to a word line(s) and an inverted word line(s) that collectively define the first input value. The SRAM cell causes a voltage and/or current difference between a bit line(s) and a complementary bit line(s) coupled to the SRAM cell. By customizing the SRAM cell to enable the XNOR function and forming a binary neural network based on the SRAM array, it is possible to effectively implement computing-in-memory (CIM) for deep neural network and machine learning applications.

Static random access memory (SRAM) cell and related SRAM array for deep neural network and machine learning applications

Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

Neuromorphic computational system(s) using resistive synaptic devices

This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

Resistive cross-point architecture for robust data representation with arbitrary precision

This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

Growing community of inventors

Tempe, AZ, United States of America

Shimeng Yu