Freescale Semiconductor,inc.

Nxp Usa, Inc.

Shilpa Gupta

Kumar Abhishek

Mukesh Bansal

Sunny Arora

Anis Mahmoud Jarrar

David Russell Tipple

Rishi Bhooshan

Hadi Ahmadi Balef

A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.

Integrated circuit with timing correction circuitry

A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Flip-flop circuit with internal level shifter

Growing community of inventors

Rohini, India

Shilpa Gupta