No. 24 Research Institute of China Electronics Technology Group Corporation

Chongqing Gigachip Technology Co. Ltd.

Shiliu Xu

Guangbing Chen

Daiguo Xu

Dongbing Fu

Jian'an Wang

Ruzhang Li

Yuxin Wang

Gangyi Hu

Tao Liu

Hequan Jiang

Lu Liu

Jie Pu

Zicheng Xu

Xueliang Xu

Zhihua Feng

Xiaoquan Yu

The comparator includes an input unit, a load unit, a control switch, and an adjustment unit. The input ends of the input unit are connected to a first input signal and a second input signal. The load unit is connected to the input unit, and the gain of the comparator is adjusted by changing the gate voltages of the pair of gain adjustment transistors of the load unit. The adjustment unit is connected to the input unit, and the gate voltages of the pair of gain adjustment transistors are adjusted according to the enable state of the control switch. The present disclosure also provides an analog-to-digital converter.

Comparator and analog-to-digital converter

The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

High-speed digital logic circuit for SAR_ADC and sampling adjustment method

The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.

High-speed and low-noise dynamic comparator

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Analogue-digital converter of non-binary capacitor array with redundant bit and its chip

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Chongqing, China

Shiliu Xu