Agency for Science, Technology and Research

Globalfoundries Singapore Pte. Ltd.

Shijie Wang

Dongzhi Chi

Ming Yang

Jianwei Chai

Juan Boon Tan

Shunqiang Gong

Mahesh Bhatkar

Daxiang Wang

Henry Medina Silva

Alex See

Lei Wang

Jinghua Teng

Zeng Wang

Lai Mun Wong

Shi Wun Tong

Yong Feng Fu

Siew Yong Leong

Carlos Manzano

A method for forming a transition metal dichalcogenide monolayer, which includes depositing a transition metal, a transition metal oxide, or a mixture thereof, on a substrate, introducing a chalcogen precursor to the transition metal, the transition metal oxide, or the mixture thereof, in the presence of an etching gas and a carrier gas at a first temperature, to form a transition metal dichalcogenide on the substrate from the transition metal, the transition metal oxide, or the mixture thereof, and subliming the transition metal dichalcogenide on the substrate in the presence of a pulsating supply of a vapor of the chalcogen precursor to form the transition metal dichalcogenide monolayer at a second temperature, wherein the vapor of the chalcogen precursor comprises a chalcogen vapor.

Method of growing monolayer transition metal dichalcogenides via sulfurization and subsequent sublimation

Herein provided is a multilayered structure including one or more nanocrystalline layers each comprising a transition metal dichalcogenide, one or more substantially amorphous electrically insulating layers each comprising a transition metal oxide, wherein the transition metal oxide comprises a transition metal which is identical to the transition metal of the transition metal dichalcogenide, wherein the one or more nanocrystalline layers and the one or more substantially amorphous electrically insulating layers are formed in an alternating manner, and wherein each of the one or more nanocrystalline layers is formed adjacent to the substantially amorphous insulating layer. A resistive memory device comprising the multilayered structure and a process of fabricating the multilayered structure are also disclosed herein.

Resistive memory device structure based on stacked layers of nanocrystalline TMDCs

Various embodiments may relate to an optical device. The optical device may include a stacked structure having a first surface and a second surface opposite the first surface. The stacked structure may include a plurality of holes or grooves extending from the first surface towards the second surface. The stacked structure may include a transition metal dichalcogenide material (TMDC) material. A thickness of the stacked structure may be of any value less than 100 nm.

Optical device and method of forming the same

A sputtering system and a sputtering method are provided. The sputtering system includes a first electrode, a magnet and a second electrode. The first electrode is an elongated tube having a first end and a second end downstream of the first end. The first end is configured to receive a gas flow and the second end is placed next to a substrate. The magnet surrounds at least a portion of the elongated tube and is configured to generate a magnetic field in a space within the elongated tube. The second electrode is disposed within the elongated tube. A voltage is configured to be applied between the first and second electrodes to generate an electric field between the first and second electrodes.

Sputtering system and method

Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

Device without zero mark layer

There is provided a multilayer coating comprising a plurality of layers comprising a) one or more layers of an elemental transition metal; b) one or more layers of an elemental metalloid; and c) two or more layers of an oxide; characterized in that the transition metal and metalloid layers are between the oxide layers and the plurality of layers does not need to contain an additional transparent conductive film (TCF). The multilayer coatings show high transparency in the visible light range combined with heat shielding without the need of transparent conductive oxide which have been previously used to achieve these properties. The multilayers can be produced with conventional physical vapor deposition methods on glass and polymer substrates. The coatings may therefore be used for applications on windows, plastic sheets and window shields. The invention relates also to the process for making the multilayer coatings, articles comprising them and their use in building and other applications.

Multilayer heat rejection coating

Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Growing community of inventors

Singapore, Singapore

Shijie Wang