Alibaba (china) Co., Ltd.

Semiconductor Manufacturing International (beijing) Corporation

Shijian Zhang

Lide Duan

Yen-kuang Chen

Huayong Hu

Qichen Zhang

The present application discloses a processor and an attack detection method thereof. The processor includes a first register and an execution unit. The execution unit is configured to: execute a first jump-related instruction under a first privilege mode; set a first field of the first register to a first jump status parameter according to execution of the first jump-related instruction; jump to a first corresponding instruction in a specified register of the first jump-related instruction; determine whether the first corresponding instruction is a legal instruction and whether a first parameter of the first corresponding instruction is equal to the first jump status parameter to obtain a first determination; and determine whether to send an alert message according to the first determination.

Processor and attack detection method thereof for detecting jump-oriented programming attack

The present application discloses a processing unit and an access detection method thereof. The processing unit includes an execution circuit. The execution circuit connects to a memory and is configured to: execute an access request, wherein the access request is for accessing at least one part of a first physical memory section corresponding to a first access base address; determine whether a first tag of the access request is equal to a second tag corresponding to the first memory base address and whether the at least one part of the first physical memory section matches a first legal access section corresponding to the first memory base address; and determine whether to send an alert message according to the determination result.

Memory access detection method

The present application discloses a computing system and an associated method. The computing system includes a memory, a master computing device and a slave computing device. The master computing device includes a memory controller and an input-output memory management unit (IOMMU). When the slave computing device accesses a first virtual address, and a first translation lookaside buffer (TLB) of the slave computing device does not store the first virtual address, the first TLB sends a translation request to the IOMMU. The IOMMU traverses page tables of the memory controller to obtain a first physical address corresponding to the first virtual address, selects and clears a first virtual address entry from a second TLB of the computing system according to a recent use time and a dependent workload of each virtual address entry to store the first virtual address and the first physical address.

Management of IOMMU TLB entries for compute units of a SIMD processing device

A mask and methods for making the mask and monitoring mask haze using the mask are provided. The mask includes chip areas that are separated by scribe lanes. A scribe lane includes a monitoring area that contains a primary pattern and an associated assist feature. The assist feature includes two parallel scattering bars. Regions in the monitoring area other than the primary pattern and the associated assist feature are covered with a phase shift layer having a transmittance smaller than that of the primary pattern and the assist feature. When the mask is exposed to a light source, the assist feature is not transferred onto a wafer but cooperates with the primary pattern to generate a primary transferred pattern on the wafer. When a region between the two scattering bars has mask haze thereon, a defect identification pattern is generated on the wafer near the primary transferred pattern following exposure.

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Beijing, China

Shijian Zhang