Applied Materials, Inc.

Lam Research Corporation

Shijian Li

Fred Conrad Redeker

Lizhong Sun

John M White

Stan D Tsai

Ramin Emami

Manoocher Birang

Tetsuya Ishikawa

Fritz C Redeker

Yezdi N Dordi

Hyungsuk Alexander Yoon

Majeed Foad

Shi-Ping Wang

Feng Quan Liu

Rashid Mavliev

John M Boyd

Yaxin Wang

Alan W Collins

Hung Chih Chen

Rajeev Bajaj

Hiroji Hanawa

Liang-Yuh Chen

Sasson Roger Somekh

Jui-lung Li

Sen-Hou Ko

David H Mai

Gary Lam

Kartik Ramaswamy

Alexander N Lerner

Thomas H Osterheld

Ratson Morad

Artur Kolics

Jianshe Tang

Boris Fishkin

Michael N Sugarman

Biagio Gallo

Brian C Lue

Seon-Mee Cho

Daniel A Carl

Tiruchirapalli Arunagiri

Haoquan Fang

Younes Achkire

Boris T Govzman

Manus K Wong

Guy Shirazi

John Boyd

Madhavi R Chandrachood

Yongqi Hu

William Thie

James V Tietz

Kapila P Wijekoon

Robert J Steger

Tony Kaushal

David Z Carman

Rahul Surana

Yongsik Moon

Raymond R Jin

Martin Scales

Dongwon Choi

Chander Radhakrishnan

Steven M Zuniga

Dan Maydan

Ashok K Sinha

Andrew J Nagengast

Farhad K Moghadam

Jay D Pinson, Ii

Alain Duboust

Derek R Witty

Yuchun Wang

Romuald Nowak

Turgut Sahin

Sidney P Huey

Kent Rossman

Lily L Pang

Timothy S Dyer

Lawrence M Rosenberg

Jayakumar Gurusamy

Troy S Detrick

Dong Hyung Lee

Kaveh F Niazi

Yutao Ma

Ramakrishna Cheboli

Kenneth D Smyth

Sandra L Rosenberg, Legal Representative

Llang-Yuh Chen

Marty Scales

Douglas Orcutt Brown

Yaxin Wong

Rashid Mavleiv

A system and method for a waferless cleaning method for a capacitive coupled plasma system. The method includes forming a protective layer on a top surface of an electrostatic chuck, volatilizing etch byproducts deposited on one or more inner surfaces of the plasma process chamber, removing volatilized etch byproducts from the plasma process chamber and removing the protective layer from the top surface of the electrostatic chuck. A capacitive coupled plasma system including a waferless cleaning recipe is also described.

Waferless clean in dielectric etch process

One or more aspects of this invention pertain to fabrication of electronic devices. One aspect of the present invention is a system for electroless deposition of metal on a substrate. According to one or more embodiments of the present invention, the system comprises a main subsystem in combination with one or more subsystems for electroless deposition on a substrate. Another aspect of the present invention is a method of making an electronic device. According to one or more embodiments of the present invention, the method comprises one or more processes. Descriptions according to one or more embodiments of the system and the processes are presented.

Apparatus for electroless metal deposition having filter system and associated oxygen source

One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.

Post-deposition cleaning methods for substrates with cap layers

Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Methods and apparatuses for three dimensional integrated circuits

Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after plating processes are provided. In particular, solutions are provided which are free of oxidizing agents and include a non-metal pH adjusting agent in sufficient concentration such that the solution has a pH between approximately 7.5 and approximately 12.0. In some cases, a solution may include a chelating agent. In addition or alternatively, a solution may include at least two different types of complexing agents each offering a single point of attachment for binding metal ions via respectively different functional groups. In any case, at least one of the complexing agents or the chelating agent includes a non-amine or non-imine functional group. An embodiment of a method for processing a substrate includes plating a metal layer upon the substrate and subsequently exposing the substrate to a solution comprising the aforementioned make-up.

Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after a plating process

Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Device with post-contact back end of line through-hole via integration

Post-deposition cleaning methods and formulations for substrates with cap layers

Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component.

Methods and systems for three-dimensional integrated circuit through hole via gapfill and overburden removal

Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Methods of post-contact back end of line through-hole via integration

Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.

Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces

The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

Methods and systems for low interfacial oxide contact between barrier and copper metallization

The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented.

Methods, apparatuses, and systems for fabricating three dimensional integrated circuits

In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluidnozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing.

Single wafer dryer and drying methods

Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.

Method for measuring dopant concentration during plasma ion implantation

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San Jose, CA, United States of America

Shijian Li