Taiwan Semiconductor Manufacturing Comp. Ltd.

ShihKuang Yang

Po-Wei Liu

Wen-Tuo Huang

Hung-Ling Shih

Yu-Ling Hsu

Yong-Shiuan Tsair

Chieh-Fei Chiu

Chen-Ming Huang

Shih-Hsien Chen

Chia-Sheng Lin

Yu-Chun Chang

Wei-Lin Chang

Yu-Hsiang Yang

Tsun-Kai Tsao

Shun-Shing Yang

A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

ONON sidewall structure for memory device and method for making the same

ONON sidewall structure for memory device and methods of making the same

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle &#x3b8;1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90&#xb0;&#x3c;&#x3b8;1&#x3c;115&#xb0; measured from the upper surface of the erase gate.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle &#x3b8;at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90&#xb0;&#x3c;&#x3b8;&#x3c;115&#xb0; measured from the upper surface of the erase gate.

Growing community of inventors

Tainan, Taiwan

ShihKuang Yang