The Boeing Company

Reme, L.l.c.

Shihchang Wu

Kyle A Woolrich

Jay Stuart Spence

Vincent T Ng

Sharon S Ng

Pedro A Martinez

Nhung T Araki

A radio frequency signal repeater includes, a first communication printed circuit board, a second communication printed circuit board, at least one embedded radio frequency module printed circuit board disposed between and communicably coupled to both the first communication printed circuit board and the second communication printed circuit board. The at least one embedded radio frequency module printed circuit board, the first communication printed circuit board, and the second communication printed circuit board are stacked one board on top of the others, and adjacent boards of the at least one embedded radio frequency module printed circuit board, the first communication printed circuit board, and the second communication printed circuit board are electrically coupled by a respective interconnection join layer so as to form an integrated printed circuit board module, where the adjacent boards are electrically coupled to each other through vias that extend through the interconnection join layer.

Multi-embedded radio frequency board and mobile device including the same

A multi-embedded radio frequency board includes a plurality of printed circuit boards stacked one on the others, at least one of the printed circuit boards of the plurality of printed circuit boards being configured so as to have a different processing function than another processing function of another printed circuit board of the plurality of printed circuit boards, and an interconnection join layer disposed between adjacent printed circuit boards of the plurality of printed circuit boards so as to physically and electrically couple the adjacent printed circuit boards to each other so as to form an integrated printed circuit board module having a predetermined radio frequency communication characteristic.

An antenna array including a printed circuit board having a plurality of printed circuit board launchers, and an array of antenna horns configured to couple with the printed circuit board, one or more antenna horns of the array of antenna horns includes a frame having at least one aperture forming a cup structure that circumscribes a respective printed circuit board launcher, the frame having a first end coupled to the printed circuit board and a second end longitudinally spaced from the first end and extending from the printed circuit board, and a plurality of compliant coupling members extending longitudinally from the first end, the plurality of compliant coupling members being coupled with respective receiving apertures of the printed circuit board such that coupling of plurality of compliant coupling members and the respective receiving apertures solely couples the one or more antenna horns to the printed circuit board.

Antenna horn, antenna, and antenna array for a radiating printed circuit board, and methods therefor

Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

High speed low power digital to analog upconverter

A duty-cycle adjustable clock generator is disclosed. Combining a fundamental sinusoidal waveform with its phase-locked second harmonic waveform generates the duty-cycle adjustable clock waveform. The clock generator maintains zero DC level and minimum reverse bias voltage swing at high microwave and millimeter wave frequencies. Proper phase shift between the fundamental and second harmonic waveforms produces the desired clock waveform. The duty-cycle is controlled by the magnitude ratio of the fundamental and phase-locked second harmonic waveforms. Due to the resulting zero DC level and minimum reverse bias voltage over the duty-cycle adjustable range, the duty-cycle adjustable clock generator can be effectively used in various microwave and optical communication systems.

Growing community of inventors

Rancho Palos Verdes, CA, United States of America

Shihchang Wu