Huawei Technologies Co., Limited

Nanyang Technological University

Fudan University

Shihai Xiao

Chen Chen

Wei Yang

Xing Hu

Florian Longnos

Junfeng Zhao

Kanwen Wang

Chuanzeng Liang

Hao Yu

Yuhao Wang

Leibin Ni

Feng Yang

Yongbing Huang

Rui Bang He

Engin Ipek

Yinyin Lin

Le Chang

Lei Fang

RenHua Yang

Yi Wei

Rui He

A memory management technology may be applied to a computer system including a dynamic random-access (DRAM). According to the memory management technology, a corresponding row management policy may be executed based on an access type of memory access, where the access type of the memory access includes a read access or a write access.

Memory management technology and computer system

A memory access technology and a computer system, where the computer system includes a memory controller and a medium controller connected to the memory controller. In the computer system, when detecting that an error occurs in first data that is returned by the medium controller in response to a first send command, the memory controller determines sequence information of the first send command in a plurality of send commands that have been sent by the memory controller within a time period from a time point at which the first send command is sent to a current time, and sends a data retransmission command to the medium controller to instruct the medium controller to resend the first data based on the sequence information.

Memory access technology and computer system

A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Memory refresh technology and computer system

A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.

A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.

Memory device and method for writing data

A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

Allocation of memory ranks based on access traffic

A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.

Method, apparatus, and non-transitory readable medium for accessing non-volatile memory

An electronic device includes a processor, a volatile memory, and a non-volatile memory. The non-volatile memory stores a first operating system, and the electronic device works in a first working mode and a second working mode. When the electronic device is in the first working mode, a second operating system is run in the volatile memory. When the processor detects that the electronic device reaches a preset condition for entering the second working mode, the non-volatile memory is enabled, and non-system data in the volatile memory is moved to the non-volatile memory. The non-system data does not include the second operating system. After the movement of the non-system data is completed, the volatile memory is disabled, and the first operating system is run in the non-volatile memory, so that the electronic device enters the second working mode.

Electronic device capable of reducing power consumption and method for reducing power consumption of electronic device

A memory access technology and a computer system, where the computer system includes a memory controller, a media controller, and a non-volatile memory (NVM) coupled to the media controller. After receiving a first read command from the memory controller, the media controller may read first data from the NVM based on a first address in the first read command. Then the media controller transmit, to the memory controller, at least two fixed-length data subblocks and metadata of the at least two data subblocks in response to at least two first send commands received from the memory controller. The metadata includes a location identifier indicating an offset of a corresponding data subblock in the first data. Thus, the memory controller obtains the first data based on the at least two data subblocks and location identifiers in the metadata.

A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

DRAM refresh method, apparatus, and system

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ror Rto indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Memory device, and data processing method based on multi-layer RRAM crossbar array

An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, &#x3c9; low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N&#x2212;&#x3c9;) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

Image recognition accelerator, terminal device, and image recognition method

This application discloses a storage system, a storage device, and a hard disk drive scheduling method. The storage system includes M disk groups, a power supply system, and a controller, and M is a natural number not less than 3. Each of the M disk groups includes at least one hard disk drive. The controller is configured to control a hard disk drive in a first disk group of the M disk groups to be in an active state to process a first group of service requests, and control a hard disk drive in a second disk group of the M disk groups to switch from the inactive state to a spin up state when the hard disk drive in the first disk group is in the active state.

Growing community of inventors

Hangzhou, China

Shihai Xiao