Macronix International Co., Ltd.

Au Optronics Corporation

General Interface Solution Limited

E Ink Holdings Inc.

Interface Optoelectronics (shenzhen) Co., Ltd.

Interface Technology (chengdu) Co., Ltd.

Interface Optoelectronics (wuxi) Co., Ltd.

Interface Optoelectronics (singzhen) Co., Ltd.

Shih-Yu Wang

Wen-Tsung Huang

Tao-Cheng Lu

Ming-Che Hsieh

Yan-Yu Chen

Chih-Wei Chu

Yu-Lien Liu

Chia-Ling Lu

Chih-Wei Hsu

Yao-Wen Chang

Ming-Yin Lee

Chieh-Wei He

Chung-Wei Liu

Yung-Sheng Chiu

Wei-Chen Tsai

Mei-Lien Huang

Seok-Lyul Lee

Wei-Ming Huang

Tun-Chun Yang

Yu-Feng Chien

Zeng-De Chen

Chun-Ta Chen

Mei-Sheng Ma

Chun-Chi Chen

Shang-Yu Huang

Qi-An Xu

Chen-You Chen

Che-Shih Lin

Wei-Cheng Cheng

Chang-Nien Mao

Shao-Chi Chen

Jung Chuan Ting

Yi-Hsin Lin

Shiuan-Huei Lin

Yu-Jen Wang

Zih-Fan Chen

Wan-Lin Li

An electrostatic discharge circuit includes a discharge switch, a first trigger circuit and a second trigger circuit. A first terminal of the discharge switch is coupled to a first power domain, and a second terminal of the discharge switch is coupled to a second power domain. The first trigger circuit is coupled between the first terminal and a control terminal of the discharge switch. The second trigger circuit is coupled between the second terminal and the control terminal. When an electrostatic discharge voltage occurs in the first power domain, the second trigger circuit is configured to form a conduction voltage between the second terminal and the control terminal to turn on the discharge switch. When the electrostatic discharge voltage occurs in the second power domain, the second trigger circuit is configured to short the second terminal and the control terminal to turn on the discharge switch.

Electrostatic discharge circuit

The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.

Electrostatic discharge protection apparatus and its operating method

Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.

Memory devices with discharging circuits

A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.

Thyristor

A display device includes a light source, a waveguide element, a liquid crystal coupler, a first holographic optical element and a second holographic optical element. The light source is configured to emit light. The waveguide element is located above the light source. The liquid crystal coupler is located between the waveguide element and the light source. The first holographic optical element is located on a top surface of the waveguide element, in which the liquid crystal coupler is configured to change an incident angle that the light emits to the first holographic optical element. The second holographic optical element is located on the top surface of the waveguide element, and there is a first distance in a horizontal direction between the first holographic optical element and the second holographic optical element, in which the second holographic optical element is configured to diffract the light to the waveguide element below.

Display device and operating method thereof

An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.

Input output circuit and electrostatic discharge protection circuit

The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.

Semiconductor device and electrostatic discharge protection method

An eye tracking device includes a substrate comprising a first substrate portion and a second substrate portion intersecting with the first substrate portion, an infrared light emitting element on the first substrate portion, and an image acquisition element on the second substrate portion. The infrared light emitting element is configured to emit infrared light to a user's eyeball. The image acquisition element and the infrared light emitting element are non-coplanar. The image acquisition element is configured to receive and sense the infrared light reflected by the eyeball for imaging.

Eye tracking device and electronic device using same

An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region, a fourth doping region and at least one junction formed by different conductivities. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the first conductivity is disposed in the first well. The second doping region having the second conductivity is disposed in the first well. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The at least one junction is formed by the first doping region and the second doping region, or formed by the third doping region and the fourth doping region.

Electrostatic discharge protection apparatus having at least one junction and method for operating the same

An ESD protection apparatus includes first and second parasitic bipolar junction transistors having different majority carriers formed in a substrate and an ESD protection device having a grounding end and a connecting end connected to the first parasitic bipolar junction transistor. When an ESD voltage applied to the ESD protection apparatus is greater than a ground voltage, a first current is grounded by passing through one of a first assembled protecting circuit including the first parasitic bipolar junction transistor and the ESD protection device and a second assembled protecting circuit including the first and the second parasitic bipolar junction transistor; and when an ESD voltage applied to the ESD protection apparatus is less than a ground voltage, a second current coming from a ground is directed to a voltage source by passing through the other one of the first assembled protecting circuit and the second assembled protecting circuit.

Electrostatic discharge protection apparatus and applications thereof

A display apparatus which is also able to receive and identify fingerprints comprises a first substrate, a second substrate, a liquid crystal layer, a plurality of dummy pixel units located in a non-display region, a fingerprint identification module, and a plurality of data extending lines. Each of the dummy units comprises first and second auxiliary electrodes. The fingerprint identification module comprises signal transmitting layer and signal receiving components on the signal transmitting layer. The signal receiving component receives reflected ultrasonic wave and converts the received waves into fingerprint signal. The data extending line is electrically connected with the dummy pixel unit. The signal receiving component transmits the fingerprint signals to the at least one first auxiliary electrode and the data extending line thus receives the fingerprint signal.

Display apparatus with fingerprint identification function

An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.

An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers.

A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.

Semiconductor structure and operation method of the same

Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

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Hsinchu, Taiwan

Shih-Yu Wang