Industrial Technology Research Institute

Ctx Opto-electronics Corp.

Shih-Yin Lin

Yung-Chang Chang

Ching-Tang Chang

Shi-Sheng Shang

Chao-Ching Hwang

Ming-Yen Lin

Chung-Kai Liu

Bing-Huang Huang

A manycore networks-on-chip (NoC) formed by a plurality of clusters is provided. The manycore NoC includes redundant routers and connection channels therefore is fault-tolerant as long as the numbers of damaged routers and damaged connection channels are under predetermined thresholds. Moreover, the NoC can retain its original logical topology without isolating any core after resetting the connection channels in response to the damaged routers and connection channels.

Manycore networks-on-chip

This invention relates to an automatic detection method and apparatus for tuning the frequency and phase of displaying clock of a display to match the frequency and phase of pixel clock of a PC's display interface card. Based on the synchronized displaying clock, the image shown by digital display will be stable and bright in color. The automatic detection apparatus of invention includes a clock generation unit, a sampling unit, a data processing unit, an accumulation unit, and a decision unit. The clock generation unit creates a plurality of sampling clocks and according to these sampling packet sequences, the sampling unit samples and holds the pixel signals of image frames based on the pixel clock of display interface card, and then stores these data in its registers. The data processing unit calculates and transmits the differences of sampled data based on every sampling clock to accumulation unit that accumulates these differences, and transmits the sums of these differences to decision unit that finds out the sampling clock with the smallest transmitted sum, and let the phase and frequency of sampling clock with the smallest summed value as those of displaying clock of the PC display.

Automatic detection method for tuning the frequency and phase of display and apparatus using the method

An apparatus for producing in a superscalar pipelined system out-of-order execution and in-order completion of a set of macroinstructions, wherein the set of macroinstructions are translated into a set of microinstructions and the microinstructions are executed by the pipelined system and wherein at least some of said macroinstructions translate into more than one microinstruction, the apparatus including a result completion register having a plurality of entry fields each of which is used to indicate a completion state of a different corresponding microinstruction among the set of microinstructions; an interrupt condition register having a plurality of entry fields each of which is used to specify an occurrence of an interrupt condition during fetching, decoding, and executing a corresponding microinstruction among the set of microinstructions; an instruction size register having a plurality of entry fields which are used to identify locations of boundaries between macroinstructions among the set of microinstructions; a priority encoder which receives input from the result completion register and the instruction size register and which during operation generates an output indicating when all of the microinstructions of a next-in-line macroinstruction have been executed; and a retirement controller which receives the output from the priority encoder and which during operation in response to the output of the priority encoder retires the next-in-line macroinstruction when said output indicates that all of the microinstructions of the next-in-line macroinstruction have been executed.

Method and apparatus for implementing precise interrupts in a pipelined

Growing community of inventors

Hsinchu, Taiwan

Shih-Yin Lin