United Microelectronics Corp.

United Mociroelectronics Corp.

Shih-Yin Hsiao

Ching-Chung Yang

Kuan-Liang Liu

Wen-Fang Lee

Kai-Kuen Chang

Chih-Chung Wang

Nien-Chung Li

Kun-Huang Yu

Ping-Hung Chiang

Chang-Po Hsiung

Shu-Wen Lin

Kuan-Chuan Chen

Chia-Min Hung

Shih-Chieh Pu

Tun-Jen Cheng

Chia-Lin Wang

Su-Hwa Tsai

Ke-Feng Lin

Chiu-Te Lee

Tzu-Yun Chang

Cheng-Hsiung Chen

Hsueh-Chun Hsiao

Shan-Shi Huang

Ming-Shun Hsu

Shih-Teng Huang

Ching-Wei Teng

Hsuan-Po Liao

Hsin-Liang Liu

Kuan-Lin Liu

Hsiu-Chin Chen

Shen-Yuan Chou

Chang-Lin Chen

Hsuan-Kai Chen

Te-Chiu Tsai

Hung-Yi Tsai

A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

Transistor structure

A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

High voltage semiconductor device and manufacturing method thereof

A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

Semiconductor device structure including high voltage MOS device

A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

Semiconductor device

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

Memory device

A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

Method for preventing dishing during the manufacture of semiconductor devices

A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.

Doping method for semiconductor device

A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

Method of forming semiconductor structure

A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.

High voltage device

A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.

Gate oxide structure and method for fabricating the same

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Chiayi County, Taiwan

Shih-Yin Hsiao