Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Industrial Technology Research Institute

Chung Shan Institute of Science and Technology

Shih-Yen Lin

Si-Chen Lee

Wei-Ting Lin

Chin-Liang Chen

Kuan-Lin Ho

Yu-Chih Liu

Samuel C Pan

Kuan-Chao Chen

Meng-Yu Lin

Chong-Rong Wu

Chi-Wen Liu

Hsuan-An Chen

Chun-Cheng Lin

Chang-Chia Huang

Xiang-Rui Chang

Xian-Rui Chang

Yu-Wei Zhang

Po-Cheng Tsai

Chien-Kuo Chang

Yi-Jen Chan

Shiang-Feng Tang

Ya-Tung Cherng

I-Min Chan

Tzu-Min Ou

Chuan-Yi Yang

Shu-Ting Chou

Chun-Yuan Huang

Shiau-Shin Cheng

Lun-Ming Lee

Chi Chen

A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.

Semiconductor device and method for forming the same

A method includes forming an interlayer dielectric (ILD) layer over a transistor; forming a first inter-metal dielectric (IMD) layer over the ILD layer; etching a via opening extending through the first IMD layer; forming a first 2-D material layer lining along sides and a bottom of the via opening; depositing a first metal in the via opening and over the first 2-D material layer; performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed; forming a second IMD layer over the first IMD layer; etching a trench in the second IMD layer; forming a second 2-D material layer lining along sides and a bottom of the trench; and depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.

Integrated circuit structure and method for forming the same

A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

Method for forming 2-D material semiconductor device with improved source/drain electrodes and gate dielectric

A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

2D crystal hetero-structures and manufacturing methods thereof

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

Semiconductor device and method of formation

The current disclosure describes semiconductor devices, e.g., transistors, include a substrate, a semiconductor region including, at the surface, MoSand/or other monolayer material over the substrate, and a terminal structure at least partially over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.

Forming semiconductor structures with two-dimensional materials

A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.

Source/drain contact with 2-D material

A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

Method of forming a semiconductor device using layered etching and repairing of damaged portions

Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

System and method for bonding package lid

The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoSand/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.

Semiconductor structures with two-dimensional materials

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

Semiconductor packaging structure and process

A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.

Growing community of inventors

Tainan, Taiwan

Shih-Yen Lin