Realtek Semiconductor Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

Chunghwa Picture Tubes, Ltd.

Energy Pass, Inc.

Shih-Wei Wang

Liang-Wei Huang

Ching-Yao Su

Sheng-Fu Chuang

Chen Ou

Chih-Chien Chang

Wen-Hsiang Lin

Peng Ren Chen

Yu-Shan Chiu

Hung-Cheng Sung

Chao-Cheng Lee

Ke-Horng Chen

Jian-Ru Lin

Te-Hsun Hsu

Hsiang-An Yang

Yen-Ming Chen

Chia-Hao Chang

Wen-Ting Chu

Gerben Doornbos

Li-Zhen Yu

Dian-Hau Chen

Georgios Vellianitis

Yue-Der Chih

Chien-Hao Chen

Matthias Passlack

Hsiang-Ku Shen

Chih-Tang Peng

Jr-Hung Li

Chi-On Chui

Chien-Ming Wu

De-Wei Yu

Yi-Shin Chu

Chien-Hsun Wang

Chi-Neng Mo

Ying-Liang Chuang

Ching-Sen Kuo

Bo-Cyuan Lu

Hsiang-Fan Lee

Tsung-Chieh Hsiao

Hung-Yi Huang

Min-Hsiu Hung

Yen-Chun Huang

Hsuan-Ting Ho

Chia-Lin Liu

Cheng-Po Chau

Huai-An Li

Cheng-Cheng Yen

Yu-Huei Lee

Chia-Tong Ho

Chia-Lin Chuang

Jin-Mu Yin

Chun-Cheng Chou

Ming-Wei Lin

Chih-Chung Chen

Su-Liang Liao

Ping-Ching Huang

Chi-Lin Chen

Yi-Jiun Lin

Derek Lin

Kuo-Wei Chu

Ching Long Lin

Wen-Cheng Luo

Wan-Chun Huang

Guan-Hong Ke

Robert Yung-His Tsu

Wei-Chan Wu

A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.

Method of manufacturing a light-emitting device

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Semiconductor device structure with salicide layer and method for forming the same

A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.

Light-emitting device

A semiconductor device includes first and second gate stack, a source/drain contact, and a first gate capping structure. The first gate stack and the second gate stack are over a semiconductor fin. The source/drain contact extends laterally from a first gate spacer of the first gate stack to a second gate spacer of the second gate stack, and extends vertically from a source/drain region in the semiconductor fin to above the source/drain region. The first gate capping structure is atop the first gate stack, and has a greater thickness on the first gate spacer of the first gate stack than on a gate metal of the first gate stack. The thickness is measured in a direction perpendicular to a top surface of the first gate stack.

FinFET structure with composite gate helmet

A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 &#x3bc;m; wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.

A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.

Fin-like field effect transistor device

An impedance matching circuit includes a variable impedance circuit, a reference voltage generating circuit and a control circuit. The variable impedance circuit is configured for coupling to a load having an impedance and has a variable impedance; the reference voltage generating circuit coupled to the variable impedance circuit is configured to receive an input voltage of the variable impedance circuit to generate a reference voltage; and the control circuit coupled to the variable impedance circuit and configured to generate a control signal according to the reference voltage and an output voltage of the variable impedance circuit to control the variable impedance to make the variable impedance match the impedance of the load.

Impedance matching circuit and integrated circuit applying the impedance matching circuit

A method includes forming gate spacers and a first interlayer dielectric (ILD) layer over a fin structure, forming a metal gate structure between the gate spacers, selectively growing a metal cap on the metal gate structure, depositing a second ILD layer over the metal cap and the first ILD layer, performing a first chemical mechanical polish (CMP) process on the second ILD layer until the metal cap is exposed, replacing the metal cap with a dielectric cap, after replacing the metal cap with the dielectric cap, etching the second and first ILD layers until source/drain regions of the fin structure are exposed, and forming source/drain contacts respectively on the source/drain regions.

Fabrication method of FinFET structure with composite gate helmet

A FinFET device includes a fin structure, a gate structure, a gate helmet, a pair of spacers and a contact structure. The fin structure protrudes from a semiconductor substrate. The gate structure crosses over the fin structure. The gate helmet includes a base and a pair of fringes. The base is disposed on a top surface of the gate structure. The pair of fringes is extended upwards from opposite sides of the base. The pair of spacers is positioned on the pair of the fringes. The contact structure is disposed between the pair of the fringes and between the pair of the spacers.

An operation voltage testing circuit includes a voltage generating circuit, a current-to-voltage conversion circuit, and a processing circuit. The voltage generating circuit is configured to generate a first voltage signal according to a first current signal, such that a photoelectric conversion unit generates a second current signal corresponding to the first voltage signal. The current-to-voltage conversion circuit is configured to generate a second voltage signal corresponding to the second current signal. The processing circuit is configured to receive the second voltage signal and to selectively adjust and output the first current signal according to the second voltage signal and a threshold value, such that the voltage generating circuit selectively adjusts the first voltage signal according to the first current signal.

Operation voltage testing circuit and method

A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.

Method for forming semiconductor device structure

A low dropout regulator includes a PMOS power transistor, a feedback network, an error amplifier and an active enhanced PSRR unit. The PMOS power transistor has a first end coupled to an input voltage, and a second end coupled to a load and the feedback network. The error amplifier receives a feedback signal generated from the feedback network, compares the feedback signal with a reference voltage to generate a difference value, and amplifies the difference value to generate an error signal. The active enhanced PSRR unit has one end coupled to the first end, and another end coupled to a control end of the PMOS power transistor and the error amplifier, detects an input voltage of the first end, and correspondingly adjusts a voltage of the control end to stabilize a voltage between the control end and the first end according to a variation of the input voltage.

Low dropout regulator with PMOS power transistor

Memory device and operation method thereof

A biasing voltage generating circuit for generating a required reverse biasing voltage of an avalanche photodiode (APD) includes: a boost power converter configured to operably convert an input voltage into a higher output voltage according to a feedback signal and a reference signal, and to apply the output voltage to be a reverse biasing voltage of the APD; a reference signal generating circuit configured to operably generate the reference signal; and a control circuit. The control circuit includes: a signal sensing circuit configured to operably generate a sensed signal corresponding to an output current of the APD; an analog-to-digital converter (ADC) configured to operably convert the sensed signal into a digital signal; and a processing circuit configured to operably adjust the feedback signal or the reference signal according to the digital signal to thereby control the boost power converter to adjust the output voltage.

Biasing voltage generating circuit for avalanche photodiode and related control circuit

A method for estimating cable length in an Ethernet system and a receiver thereof are applicable to an Ethernet system. The method for estimating cable length includes obtaining a channel tap from channel information of a feedback equalizer in the Ethernet system and estimating a cable length according to the channel tap, a first coefficient and a constant.

Method for estimating cable length in Ethernet system and receiver thereof

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Hsinchu, Taiwan

Shih-Wei Wang