Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Wei Peng

Jiann-Tyng Tzeng

Wei-Cheng Lin

Kam-Tou Sio

Charles Chew-Yuen Young

Chih-Ming Lai

Chih-Liang Chen

Te-Hsin Chiu

Chia-Tien Wu

Ru-Gun Liu

Wei-An Lai

Hui-Ting Yang

Hui-Zhong Zhuang

Cheng-Chi Chuang

Chun-Kuang Chen

Guo-Huei Wu

Pin-Dai Sue

Shun Li Chen

Li-Chun Tien

Yung-Sung Yen

Ching-Yu Huang

Shun-Li Chen

Te-hsin Chiu

Tien-Lu Lin

Wen-Hao Chen

Chi-Yeh Yu

Lipen Yuan

Wei-Chen Chien

Ching-Wei Tsai

Lee-Chung Lu

Ken-Hsien Hsieh

Yi-Hsun Chiu

Lei-Chun Chou

Meng-Hung Shen

Chih-Min Hsiao

Kam-tou Sio

Wei-cheng Tzeng

Hui-ting Yang

Jay Yang

Chung-Hsing Wang

Yi-Kan Cheng

Hou-Yu Chen

Yuan-Te Hou

Yu-Xuan Huang

Shang-Wen Chang

Kuan-lun Cheng

Ching-Hsu Chang

Chew-Yuen Young

Chun-Hung Liou

Jiun-Wei Lu

Meng-hung Shen

Ming Chian Tsai

Hui-Ting Yang′

Yu-rong Chen

Sheng-Feng Huang

A semiconductor device includes first and second conductive layers, a first epitaxial structure and a first via structure. The first conductive layer extends along a first direction, and provides a first reference voltage signal. The second conductive layer extends along the first direction, and is separated from the first conductive layer along a second direction. The first epitaxial structure is disposed between the first conductive layer and the second conductive layer, and has a first width along the first direction. The first via structure is disposed between the first conductive layer and the second conductive layer, and transmits the first reference voltage signal from the first conductive layer through the second conductive layer to the first epitaxial structure. The first via structure has a second width along the first direction. The second width is approximately equal to or larger than twice of the first width.

Semiconductor device

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a first electrical conductor, a second electrical conductor, a third electrical conductor, a plurality of metal features and a plurality of active regions. The first electrical conductor extends along a first direction and is electrically coupled to a first voltage. The second electrical conductor extends along the first direction and is electrically coupled to a second voltage. The second voltage is lower than the first voltage. The third electrical conductor extending along the first direction is electrically coupled to a third voltage and disposed between the first electrical conductor and the second electrical conductor. The metal features extend along a second direction perpendicular to the first direction and are formed above the first electrical conductor, the second electrical conductor and the third electrical conductor.

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.

Semiconductor devices and methods of manufacturing thereof

A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

APR placement for hybrid sheet cells

An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Backside conductive segments cover a first active region and define an opening above a second active region

Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Methods for generating a circuit with high density routing layout

An integrated circuit includes a first power rail, a second power rail, and a power tap cell. The first power rail is at a first side of the integrated circuit. The second power rail is at a second side of the integrated circuit. The first and second sides are on opposite sides of at least a complementary field effect transistor. The power tap cell is coupled to the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail.

Integrated circuits and methods for power delivery

A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

Semiconductor device including vertical transistor with back side power structure

An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

Integrated circuit

An integrated circuit includes metal rails. The integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. The integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. The integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. The integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.

Integrated circuit with backside power rail and backside interconnect

An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Deep lines and shallow lines in signal conducting paths

A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Three dimensional integrated circuit with monolithic inter-tier vias (MIV)

A semiconductor structure including a first conductive layer, a second conductive layer situated above the first conductive layer, and a via extending diagonally between the second conductive layer and the first conductive layer to electrically connect the first conductive layer to the second conductive layer.

Diagonal vias in semiconductor structures

An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Mixed poly pitch design solution for power trim

Growing community of inventors

Hsinchu, Taiwan

Shih-Wei Peng