Intel Corporation

Shih-wei Liao

Gansha Wu

Guei-Yuan Lueh

Hong Wang

Xinmin Tian

Milind Baburao Girkar

Perry H Wang

Daniel M Lavery

Gerolf F Hoflehner

Zhao Hui Du

Dongkeun Kim

John Thomas Shen

John P Shen

Sanjiv M Shah

Gautham N Chinya

Richard A Hankins

Trung Am Diep

Paul M Petersen

Ryan N Rakvic

Jinzhan Peng

Zhiwei Ying

Zhaohui Du

Bu Qi Cheng

Grant E Haab

Hideki Saito

Ken Lueh

Daniel LaVery

Gerolf Hoflehner

Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

Methods and apparatuses for compiler-creating helper threads for multi-threading

Method, apparatus and system embodiments to schedule user-level OS-independent 'shreds' without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.

Compiler-based scheduling optimization hints for user-level threads

A method including providing a stream of content to a processor, transforming kernels within the stream of content through affine modeling, transforming the affine modeled kernels, stream contracting kernel processes, and stream blocking the kernel processes.

Computation transformations for streaming applications on multiprocessors

Systems and methods perform affine partitioning on a code stream to produce code segments that may be parallelized. The code segments include copies of the original code stream with conditional inserted that aid in parallelizing code. The conditional is formed by determining the constraints on a processor variable determined by the affine partitioning and applying the constraints to the original code stream.

Systems and methods for affine-partitioning programs onto multiple processing units

Code is affine partitioned to generate affine partitioning mappings. Parallel code is generated based on the affine partitioning mappings. Generating the parallel code includes coalescing loops in the parallel code generated from the affine partitioning mappings to generate coalesced parallel code and optimizing the coalesced parallel code.

Generating efficient parallel code using partitioning, coalescing, and degenerative loop and guard removal

Linear transformations of statements in code are performed to generate linear expressions associated with the statements. Parallel code is generated using the linear expressions. Generating the parallel code includes splitting the computation-space of the statements into intervals and generating parallel code for the intervals.

Splitting the computation space to optimize parallel code

Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

Methods and apparatuses for thread management of multi-threading

Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Methods and apparatus for reducing memory latency in a software application

Growing community of inventors

San Jose, CA, United States of America

Shih-wei Liao