Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih Ting Lin

Jing-Cheng Lin

Chen-Hua Douglas Yu

Szu-Wei Lu

Shin-Puu Jeng

Szu Wei Lu

Wen-Chih Chiou

Shang-Yun Hou

Hsin Chang

Chi-Hsi Wu

Kuo-Chiang Ting

Weiming Chris Chen

Kung-Chen Yeh

Jui-Pin Hung

Cheng-Lin Huang

Weng-Jin Wu

Tsung-Fu Tsai

Jin-Cheng Lin

Justin Huang

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

Integrated circuit package and method

A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

Integrated fan-out structure with rugged interconnect

A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.

Solution for reducing poor contact in InFO package

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Carrier warpage control for three dimensional integrated circuit (3DIC) stacking

A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.

Rework process and tool design for semiconductor package

Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.

Growing community of inventors

Taipei, Taiwan

Shih Ting Lin