Powerchip Semiconductor Manufacturing Corporation

Industrial Technology Research Institute

Powerchip Technology Corporation

Prokia Technology Co., Ltd

Shih-Ping Lee

Shyng-Yeuan Che

Hsiao-Pei Lin

Po-Yi Wu

Kuo-Fang Huang

Bo-An Tsai

Ya-Ting Chen

Pin-Chieh Huang

Yi-Ping Lin

Hung-Hsiu Yu

Jui-Hung Hung

Yu-An Chen

Chi-Nan Chen

Wen-Hao Huang

Cheng-Han Yang

Yi-Chen Yeh

Yu-Cheng Lu

Yu-Ching Liao

Hsin-Ying Tung

Wen-Hsien Chen

Yeh-Yu Chiang

Kuo-Kang Liu

Yu-Chun Huo

Cheng-Zuo Han

Fu-Ming Chuang

Tung-Chuan Wu

Han-Wen Tsai

Chih-Ping Chung

Chin-Chung Nien

Yu-Liang Chung

Jinn-Chou Yoo

Ming-Wei Chang

Shu Huang

Fang Chuan Ho

Ran-Jin Lin

Sheng-Hsiung Chan

Hsiu-Hsiang Chen

Yi-Jen Tsou

Ming-Hsiu Hsu

Rong-Ho Lee

Gwo-Shiang Lee

Shih-Hsorng Shen

Tsang-Fang Jeng

Chun-Ta Chen

Sung-Tao Lin

Kuo Hsiung Chen

Han-Jou Li

Chia-Hsien Kuo

Hen-Diong Kng

Hao-Yan Wu

Hsiu-Wen Huang

Chuan-Hua Chang

Tse-Hsien Wu

Shih-Siang Chen

Yu-Hsiang Chien

Yi-Nung Lin

Jhih Fan Tu

Chun-Fu Wu

Chang Tsung Lin

Chen-Tso Han

Chih Feng Sung

Ming-Jui Tsai

Hirokazu Fujimaki

Chih-Wei Su

Chia-Hao Yu

Mao-Hsing Chiu

A wafer processing method including following steps is provided. A release layer is formed on a first wafer. An adhesive layer is formed on a second wafer. One of the first wafer and the second wafer is a device wafer. The device wafer includes a valid die region and a trimming region. A handler is applied to place the first wafer on the second wafer, so that the release layer and the adhesive layer are bonded to each other, and the adhesive layer completely covers the valid die region. During the process of placing the first wafer on the second wafer, the handler directly moves the first wafer.

Wafer processing method

A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A first dielectric layer is formed on the substrate. A first conductive layer is formed in the first dielectric layer. A capping layer is formed on the first dielectric layer and the first conductive layer. The material of the capping layer is nitride. A diffusion barrier layer covering the capping layer is formed. The material of the diffusion barrier layer is silicon-rich oxide (SRO). A second dielectric layer is formed on the diffusion barrier layer. An opening is formed in the second dielectric layer. The opening exposes the diffusion barrier layer. A patterned photoresist layer is formed on the second dielectric layer. A patterning process is performed by using the patterned photoresist layer as a mask to expand the opening and to expose the first conductive layer.

Manufacturing method of semiconductor structure

An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

Image sensor structure

A semiconductor structure including the following components is provided. A first device structure includes a first substrate, a first dielectric structure, a first landing pad, and a first capping layer. A second device structure is disposed on the first device structure. The second device structure includes a second substrate, a second dielectric structure, a stop layer, and a second landing pad. The thickness of the stop layer is greater than the thickness of the first capping layer. A first TSV structure is disposed in the second substrate, the second dielectric structure, and the first dielectric structure. The first TSV structure passes through the first capping layer and is electrically connected to the first landing pad. A second TSV structure is disposed in the second substrate and the second dielectric structure. The second TSV structure passes through the stop layer and is electrically connected to the second landing pad.

Semiconductor structure and manufacturing method thereof

A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.

Capacitor structure and manufacturing method thereof

A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

LDMOS with polysilicon deep drain

The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

Image sensing module

A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.

Solid-state image sensor with pillar surface microstructure and method of fabricating the same

A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.

Through silicon via and method of manufacturing the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.

A robot arm including a first joint, a second joint, and a coupling element is provided. The first joint has a first inclined surface. The second joint is jointed to the first joint and has a second inclined surface. The coupling element has a third inclined surface and a fourth inclined surface opposite to the third inclined surface, wherein the third inclined surface contacts the first inclined surface, and the fourth inclined surface contacts the second inclined surface.

Robot arm, mechanical assembly and assembly method thereof

A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.

Manufacturing method of image sensor

A solid-state image sensor with pixels each including a photoelectric conversion portion made of a second type doped semiconductor layer and a semiconductor material layer, and the second type doped semiconductor layer contacts a first type doped semiconductor substrate. An anti-reflective portion is provided with multiple micro pillars on the semiconductor material layer, wherein micro pillars are isolated by recesses extending into the photoelectric conversion portion, and the refractive index of the micro pillar gradually decreases from bottom to top and is smaller than the refractive index of the light-receiving portion of the semiconductor material layer.

Growing community of inventors

Hsinchu, Taiwan

Shih-Ping Lee