Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Ping Hong

Ming-Tsung Wu

Han-Hui Hsu

Hong-Ji Lee

Yuan-Chieh Chiu

Hsiang-Lan Lung

Yen-Hao Shih

Kuang-Chao Chen

Yu-Cheng Liu

Chun-Min Cheng

Yu-Chung Chen

Shih-Chin Lee

Yen-Ju Chen

Fang-Hao Hsu

Yao-An Chung

An-Chi Wei

ChiaHua Ho

Chen-Hsiang Lu

Chia-Hua Ho

Ta-Hung Yang

Shih-Hao Chen

An-Chyi Wei

Ta Hung Yang

Hung-Bin Lin

Chien-Yu Wang

Kuo-Liang Wei

Ping-Chung Lee

Fa-Chih Liu

Yen-Lu Chen

Ching-Hsiung Li

An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.

Plasma etcher edge ring with a chamfer geometry and impedance design

Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Method of fabricating semiconductor device

A method for cleaning a substrate is provided. The method includes providing a substrate. Metal compound residues are formed over the substrate. The method includes exposing the substrate to an organic plasma to volatilize the metal compound residues. The organic plasma is generated from a gas. The gas includes an organic gas, and the organic gas is made of a hydrocarbon compound or an alcohol compound.

Method for cleaning substrate

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes an isolation feature over the semiconductor substrate. The fin structure is surrounded by the isolation feature. The semiconductor device structure further includes a gate stack covering the fin structure. In addition, the semiconductor device structure includes a source or drain (S/D) structure covering the fin structure. The semiconductor device structure also includes a conductive contact connected to the S/D structure. The conductive contact includes a first portion and a second portion. The second portion extends from the first portion to the S/D structure. The first portion has a first width adjoining the second portion. The second portion has a second width greater than the first width.

Structure and formation method of semiconductor device structure

Semiconductor device and method of fabricating the same

A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

Inverted-T shaped via for reducing adverse stress-migration effects

Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

Memory device and method of forming the same

A method for cleaning a plasma processing chamber is provided. The method includes introducing an organic gas into a plasma processing chamber. The organic gas includes an organic compound including carbon and hydrogen. The method includes generating an organic plasma by exciting the organic gas. The organic plasma reacts with metal compound residues over an interior surface of the plasma processing chamber to volatilize the metal compound residues into a gaseous metal compound. The method includes removing the gaseous metal compound from the plasma processing chamber.

Method for cleaning plasma processing chamber and substrate

A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures.

Vertical and 3D memory devices and methods of manufacturing the same

Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Memory device and method of manufacturing the same

A NAND-based non-volatile memory contact structure includes a trench located adjacent to layered alternating conducting and insulating layers, the layers lining sides and bottom of the trench. A portion of the trench is removed to expose a surface in which electrical connections to the conducting layers are provided on one level.

Contact structure for NAND based non-volatile memory device and a method of manufacture

A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Method of shaping densely arranged PL gates and peripheral MOS gates for ILD oxide fill-in

A patterning method is provided. First, a substrate having an objective material layer thereon is provided. Thereafter, a mask layer is formed on the objective material layer. Afterwards, a patterned layer is formed over the mask layer, wherein a material of the patterned layer includes a metal-containing substance. Then, the mask layer is patterned to form a patterned mask layer. Further, the objective material layer is patterned, using the patterned mask layer as a mask.

Patterning method

A method of forming a semiconductor structure is provided. First, a target layer and a mask layer are sequentially formed on a substrate. Thereafter, a first pattern transfer layer having a plurality of openings is formed on the mask layer. Afterwards, a second pattern transfer layer is formed in the openings of the first pattern transfer layer. The mask layer is then patterned, using the first pattern transfer layer and the second pattern transfer layer as a mask, so as to form a patterned mask layer. Further, the target layer is patterned using the patterned mask layer.

Semiconductor structure and method of fabricating the same

A method for patterning a material is provided. The method includes patterning a second material over a first material over a substrate. A surface portion of the patterned second material is converted to form a third material and a remaining patterned second material, wherein the third material is around the remaining patterned second material. One of the remaining patterned second material and the third material is removed to form a mask. The first material is patterned by using the mask.

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Hsinchu, Taiwan

Shih-Ping Hong