Actel Corporation, Inc.

Intel Corporation

Shih-Ou Chen

John L McCollum

Steve S Chiang

Amr M Mohsen

Leopoldo D Yau

Esmat Z Hamdy

Yih S Lin

John L McCullum

Electrically-programmable low-impedance antifuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or metal having a barrier metal underneath. At least one of the two electrodes of each antifuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer.

Electrically-programmable low-impedance anti-fuse element

Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the antifuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed.

A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remians in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalanching a junction associated with it. In a preferred embodiment, a buried contact if formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor. Alternatively, a weak portion in the dielectric may be deliberately created by placing a lightly doped N-type diffusion in the area under which the buried contact is desired.

Structure for protecting thin dielectrics during processing

An electrically programmable antifuse element incorporates a composite interlayer of dielectric material and amorphous silicon interposed between two electrodes. The lower electrode may be formed from a refractory metal such as tungsten. Preferably, a thin layer of titanium is deposited over the tungsten layer and its surface is then oxidized to form a thin layer of titanium oxide which serves as the dielectric material of the composite dielectric/amorphous silicon interlayer. A layer of amorphous silicon is then deposited on top of the titanium oxide dielectric to complete the formation of the composite interlayer. A topmost layer of a refractory metal such as tungsten is then applied over the amorphous silicon to form the topmost electrode of the antifuse.

Electrically programmable antifuse element incorporating a dielectric

A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remains in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalancing a junction associated with it. In a preferred, embodiment, a buried contact is formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor. Alternatively, a weak portion in the dielectric may be deliberately created by placing a lightly doped N-type diffusion in the area under which the buried contact is desired.

An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.

Plasma enhanced chemical vapor deposited vertical silicon nitride

An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silcon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions. A subsequent annealing process involving controlled temperatures and cycle times provides for determining desired resistive values from an equivalent deposition process. Further, a barrier metal layer may be formed between the vertical resistor and the second conductive region.

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Fremont, CA, United States of America

Shih-Ou Chen