United Microelectronics Corp.

Shih-Ming Kuo

Ming-Jui Chen

Te-Hsien Hsieh

Jing-Yi Lee

Cheng-Te Wang

Ping-I Hsieh

Yung-Feng Cheng

Te-Hung Wu

Hui-Fang Kuo

Yu-Shiang Yang

Chuen Huei Yang

Yan-Chun Chen

Hsiang-Yun Huang

Lun-Hung Chen

A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Method for optimizing an integrated circuit layout design

A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.

Method of optical proximity correction according to complexity of mask pattern

A method for making a photomask layout is disclosed. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.

Method for making photomask layout

A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.

Double patterning mask set and method of forming thereof

A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.

Method for selectively amending layout patterns

Growing community of inventors

Tainan, Taiwan

Shih-Ming Kuo