Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Ming Chin

Hsiao-Chi Huang

Han-Ming Liang

Hsiu-Mei Yu

Chun-Jung Huang

Chia-Jen Cheng

Yu-Yao Huang

Fang-Chuang Liu

A system includes a first mask, a second mask and a mask container. The first mask includes a first identification code and a second identification code. The second mask includes a third identification code and a fourth identification code. The mask container is configured to store the first mask and the second mask. The first identification code is different from the third identification code. In response to a pattern, for performing a photolithography process, on the first mask, that is different from a pattern on the second mask, the second identification code is different from the fourth identification code. In response to the pattern on the first mask being the same as the pattern on the second mask, the second identification code is the same as the fourth identification code.

Semiconductor process system and method

A system includes a plurality of masks and a scanner device. A pattern of a semiconductor device is defined by each of the plurality of masks in a photolithography process. A first mask of the plurality of masks includes a first identification code configured to distinguish the first mask from remaining masks of the plurality of masks. The scanner device is configured to read the first identification code to select the first mask from the plurality of mask, in order to form the pattern of the semiconductor device on a substrate according to the first mask.

A reticle purging system includes an automated pod opener, a reticle holding device, a reticle transporting device and at least one purging device. The reticle holding device has a reticle occupiable zone thereon. The reticle transporting device is assigned with a transportation path from the automated pod opener to the reticle holding device. The reticle occupiable zone is exposed to the purging device.

Reticle purging system and method thereof

A method for improving an adhesion bond between a solder material and an under bump metallization (UBM) layer including providing at least two UBM layers overlying a chip bonding pad including an uppermost UBM layer forming a contact layer for forming a solder bump thereon; depositing a solder bump precursor material overlying the contact layer to form a solder column; exposing the sidewalls of the solder column to include the contact layer sidewalls; oxidizing the contact layer sidewalls to form a contact layer sidewall oxide at a temperature lower than the melting point of the solder bump precursor material; and forming a solder bump by reflowing the precursor material to wet the contact layer surface to exclude the contact layer sidewalls.

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Nantou County, Taiwan

Shih-Ming Chin