Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Cubtek Inc.

Shih-Ming Chang

Ru-Gun Liu

Chih-Ming Lai

Ken-Hsien Hsieh

Tsai-Sheng Gau

Ming-Feng Shieh

Chi-Lun Lu

Wen-Chuan Wang

Chih-Jie Lee

Wen Lo

Shau-Lin Shue

Chin-Hsiang Lin

Chung-Ju Lee

Tien-I Bao

Sheng-Chi Chin

Shuo-Yen Chou

Chien-Cheng Chen

Hui-Zhong Zhuang

Jyu-Horng Shieh

Yung-Sung Yen

Chia-Ying Lee

Tsong-Hua Ou

Ting-Wei Chiang

Hsin-Chang Lee

Chia-Jen Chen

Jung-Chan Yang

Yu-Xuan Huang

Yi-Hsiung Lin

Guo-Huei Wu

Yu-Jung Chang

Pochun Wang

Ya-Chi Chou

Chih-Cheng Chin

Wei-Liang Lin

Hung-Chang Hsieh

Chun-Hung Liu

Chien-Wen Lai

Chin-Yuan Tseng

Tran-Hui Shen

Chiu-Hsiang Chen

Chen-Shao Hsu

Chia-Hao Yu

Wen-Chun Huang

Cheng-Hsiung Tsai

Shih-Chun Huang

Chang-Cheng Hung

Chung-Hsing Chang

Minfeng Chen

Dong-Yo Jheng

Ching-Yu Chang

Jeng-Horng Chen

Shinn-Sheng Yu

Chih-Tsung Shih

Chun-Kuang Chen

Yuan-Te Hou

Chien-Chih Chen

Kuei-Liang Lu

Yu-Po Tang

Ping-Chieh Wu

Chia-Hua Chang

Chih-Min Hsiao

Hsin-Wei Wu

Jue-Chin Yu

Tzu-Chun Lo

Chung-Te Lin

Shang-Chieh Chien

Anthony Yen

Shy-Jay Lin

Kuei-Shun Chen

Chia-Chen Chen

Hua-Tai Lin

Yu-Tien Shen

Yu-Chen Chang

Hung Chang Hsieh

Jui-Ching Wu

Chien Wen Lai

Shao-Chi Wei

Fang-Yu Fan

Xiangdong Chen

Erik S Jeng

Chi-Yu Lu

Jerry Chang Jui Kao

Chun-Yu Lin

Chun-Yen Chang

Cheng-I Huang

Yung-Chen Chien

Chien-Hsun Chen

Joy Cheng

Ying-Chou Cheng

Han-Wei Wu

Tzu-Chin Lin

Meng-Wei Chen

Bi-Ling Chen

Kuan-Hsin Lo

Chen-Hau Wu

Chin-Min Huang

Chia-Cheng Chang

Cherng-Shyan Tsay

Yi-Jie Chen

Jan-Wen You

In a method of tool matching, aberration maps of two or more optical systems of two or more scanner tools are determined. A photoresist pattern is generated by projecting a first layout pattern by an optical system of each one of the two or more scanner tools on a respective substrate. One or more Zernike coefficients of the two or more optical systems are adjusted based on the determined aberration maps of the two or more optical systems to minimize critical dimension (CD) variations in a first region of the photoresist patterns on each respective substrate.

Tool mismatch reduction using aberration map of the tools

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

Geometric mask rule check with favorable and unfavorable zones

An illumination system includes a plurality of pixels (or spots) that are (or may be) configured in one or more polarization configuration types. The pixels of the illumination system may be configured to promote particular types of polarization (e.g., transverse electric (TE) polarization, transvers magnetic (TM) polarization) to increase pattern contrast while achieving suitable exposure operation throughput. Moreover, the pixels of the pixels of the illumination system may be configured to achieve free-form (arbitrary or freely-configurable) polarization, which permits the polarization of radiation to be tailored to particular exposure operation patterns and other parameters.

Semiconductor processing tool and methods of operation

A method includes generating an electron beam from a radiation source; modifying an energy distribution of the electron beam through a first shaping aperture; and exposing a substrate to portions of the electron beam passing through the first shaping aperture. The first shaping aperture comprises blocking strips with a plurality of slots therebetween, a frame surrounding the blocking strips, and a diagonal support connected to the frame and one of the blocking strips.

Semiconductor apparatus and method of operating the same

A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.

System and method for selecting photolithography processes

An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Integrated circuit and method of manufacturing same

A mirror structure includes an insulator layer and a first conductive layer disposed on the insulator layer. The first conductive layer includes a first non-conductive film disposed on the insulator layer. The first non-conductive film includes one or more first conductive segments. The mirror structure also includes a reflective layer disposed on the first conductive layer and an electro optical layer disposed on the reflective layer. The mirror structure further includes a second conductive layer disposed on the electro optical layer. The second conductive layer includes a second non-conductive film disposed on the electro optical layer. The second non-conductive film includes one or more second conductive segments.

Method for generating EUV radiation

In a method of manufacturing a semiconductor device, a first conductive pattern and a second conductive pattern are formed over the first conductive pattern, in a first interlayer dielectric (ILD) layer disposed over a substrate. The second conductive pattern contacts the first conductive pattern. A space is formed in the first ILD layer by removing a part of the second conductive pattern to expose a part of the first conductive pattern. The space is filled with a dielectric material. A third conductive pattern is formed over a remaining portion of the second conductive pattern. A via contact connecting the first conductive pattern and the third conductive pattern is formed by patterning the remaining portion of the second conductive pattern as an etching mask.

Semiconductor device and manufacturing method thereof

In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Method of manufacturing photo masks

A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Optical proximity correction and photomasks

A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Semiconductor structure and method for forming the same

In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns.

Method of manufacturing a via and a metal wiring for a semiconductor device

In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.

Semiconductor device and manufacturing method thereof including a conductive-material etching process to further adjust a via shape

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Semiconductor structures and method for manufacturing the same

An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Buried metal track and methods forming same

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Hsinchu County, Taiwan

Shih-Ming Chang