Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Lien Linus Lu

Cheng-En Lee

Yu-Der Chih

Jui-Che Tsai

Cormac Michael O'Connell

Saman M I Adham

Sai-Hooi Yeong

Kun-Hsi Li

Chien-Chen Lin

Yu-Ming Lin

Yih Wang

Bo-Feng Young

Yi-Chun Shih

Cheng Hung Lee

Yen-Huei Chen

Chia-En Huang

Chao-I Wu

Jonathan Tsung-Yung Chang

Chia-Fu Lee

Chih-Yu Lin

Wei Min Chan

Wei-Min Chan

Chung-Cheng Chou

Katherine H Chiang

Fong-Yuan Chang

Yu-Hao Hsu

Chen-Lin Yang

Chia-en Huang

Chien-Yin Liu

Kuan-Chun Chen

Hsueh-Chih Yang

Peter Noel

Shih-Liang Wang

Ramin Shariat-Yazdi

Han-Jong Chia

Ming-Hsien Lin

Tong-Chern Ong

Anthony Oates

Johnathan Tsung-Yung Chang

Hidehiro Fujiwara

Hiroki Noguchi

Yi-Ju Chen

Saman Adham

Shou-Chung Lee

Chen-En Lee

Lorraine Wang

Ramin Shariat-yazdi

Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.

Systems and methods for classifying puf signature modules of integrated circuits

Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.

Systems and methods to store multi-level data

Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

Integrated circuit (IC) signatures with random number generator and one-time programmable device

An integrated circuit layout is provided. The integrated circuit layout includes: a first active region having a first plurality of field effect transistors (FETs); and an interconnect contacting sources and drains of the first plurality of FETs in the first active region through a first set of contact structures. At least one of the first set of contact structures is electrically non-conductive.

Integrated circuit layout, integrated circuit, and method for fabricating the same

Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

Buffer control of multiple memory banks

Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.

Physical unclonable function (PUF) security key generation

Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.

Method and apparatus for protecting a PUF generator

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.

Method for PUF generation using variations in transistor threshold voltage and subthreshold leakage current

An integrated circuit includes a first set of inverters configured to receive a first set of check bits, and to generate a second set of check bits, a first memory cell array including a first portion of memory cells configured to store a first set of data, and a second portion of memory cells configured to store the second set of check bits, a second set of inverters to receive a third set of check bits, and to generate a fourth set of check bits, and an error correction code decoder configured to detect or correct an error in a second set of data or the fourth set of check bits thereby generating a set of output data and a been-attacked signal. The second set of data corresponds to the first set of data. The been-attacked signal indicates a reset attack by a user.

Integrated circuit and method of operating same

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.

Method and apparatus for noise injection for PUF generator characterization

A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

SRAM power-up random number generator

Disclosed herein are related to an age detector for determining an age of a memory block, and a method of operation of the age detector. In one configuration, a memory system includes a memory block and an age detector coupled to the memory block. In one aspect, the memory block generates a first set of data in response to a first power on, and generates a second set of data in response to a second power on. In one configuration, the age detector includes a storage block to store the first set of data from the memory block, and inconsistency detector to compare the first set of data and the second set of data. In one configuration, the age detector includes a controller to determine an age of the memory block, based on the comparison.

Memory block age detection

Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

PUF method and structure

A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix (G matrix) formed of a concatenation of a parity matrix (P matrix) and an identity matrix; determining a number of rows in the P matrix for a truncated P matrix in view of a correcting strength and a number of data bits; selecting a first subset of rows and a second subset of rows in the P matrix, wherein a first sum of row weights of each row in the first subset of rows is equal to or less than a second sum of row weights of each row in the second subset of rows; and generating the truncated P matrix by keeping the first subset of rows of the P matrix so as to minimize a number of logic gate operations.

System and method of reducing logic for multi-bit error correcting codes

A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Memory device having bitline segmented into bitline segments and related method for operating memory device

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Hsinchu, Taiwan

Shih-Lien Linus Lu