Intel Corporation

Duke University

Shih-Lien L Lu

Vivek K De

Dinesh Somasekhar

Wei Wu

Muhammad M Khellah

Yibin Ye

Stephen H Tang

Fabrice Paillet

Shigeki Tomishima

Ali Keshavarzi

Christopher B Wilkerson

Helia A Naeimi

James W Tschanz

Charles Augustine

Zeshan A Chishti

Chris Wilkerson

Kenneth J Janik

Michael F Miller

Alaa R Alameldeen

Nam Sung Kim

Seth H Pugsley

Keith A Bowman

Christopher J Hughes

Tanay Karnik

Sanjeev Kumar

Konrad K Lai

Janice C Lee

David Champagne

Abhishek Tiwari

Edward Thomas Grochowski

Steven Hsu

Kingsum Chow

Murali M Annavaram

Peng-Fei Chuang

Robert L Scott

Ralph Nathan

Brian S Doyle

Suman Datta

Ram K Krishnamurthy

Zhe Wang

Aamer Jaleel

Daniel J Sorin

Georgios Panagopoulos

Zeev Sperber

Siddhartha Chhabra

Siva G Narendra

Carlos V Rozas

Francis X Mckeen

Ravishankar Iyer

Rajat Agarwal

Bin Xing

Krystof C Zmudzinski

Herbert H Hum

Srikanth T Srinivasan

Scott H Robinson

Srihari Makineni

Zhen Fang

John L Gustafson

Mark Shanahan

Henry Stracovsky

Chia-Lin Yang

Guy Patkin

Khun Ban

Ying-Chen Lin

Sagi Lahav

Ishwar Singh Bhati

James Tachanz

Tanay Karnlk

Technologies for software attack detection include a computing device with a processor and a memory external to the processor. The processor originates a memory transaction with an associated secure enclave status bit that indicates whether the memory transaction originated in a secure execution mode, such as from a secure enclave. The processor computes an error-correcting code (ECC) based as a function of memory transaction data and the secure enclave status bit, and performs the memory transaction based on the ECC and the memory transaction data using the memory of the computing device. The processor may store the ECC and the memory transaction data to memory. The processor may load a stored ECC and data from the memory and compare the computed ECC to the stored ECC to detect memory transactions with an invalid secure enclave status bit. Other embodiments are described and claimed.

Technologies for software attack detection using encoded access intent

In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Bitcell state retention

Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

Adaptive error correction in memory devices

An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Magnetic storage cell memory with back hop-prevention

An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory

Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

DRAM data path sharing via a split local data bus

A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

Method and apparatus for pre-fetching data in a system having a multi-level system memory

A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Instruction and logic for run-time evaluation of multiple prefetchers

Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.

DRAM data path sharing via a segmented global data bus

Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Sequential circuit with error detection

Techniques are described that includes using a memory to store data within a system. The techniques include lowering a supply voltage applied to said memory and ceasing use of the memory to store data within the system. The techniques further include reading values from the memory with the supply voltage being lowered. The techniques further include determining a radiation level from an amount of corrupted ones of the values.

Memory with enhancement to perform radiation measurement

Provided are a memory device and a memory bank comprising a split local data bus, and a segmented global data bus coupled to local data bus. Provided also is a method comprising, receiving a signal from a split local data bus, and transmitting the signal to a segmented global data bus coupled to local data bus. Provided also is a computational device that includes the memory device and the memory bank, and optionally one or more of a display, a network interface, and a battery.

DRAM data path sharing via a split local data bus and a segmented global data bus

An apparatus comprises: a source array of memory cells with associated source sense amplifiers; a destination array of memory cells with associated destination sense amplifiers; and logic to activate a source word-line (WL) to select a row of memory cells within the source array such that data in the selected row of memory cells is latched by the associated source sense amplifiers, wherein the logic to activate a destination WL to select a row of memory cells within the destination array such that data in the selected row of memory cells is latched by the associated destination sense amplifiers, and wherein the source and destination arrays of memory cells are within a same bank of a memory.

Apparatus and method for page copying within sections of a memory

Embodiments include apparatuses and systems including a circuit which increases a speed of removal of data stored in a memory cell. In embodiments, the circuit includes a first discharge device coupled to an access transistor of a memory cell and coupled to an output terminal of a charge pump circuit to pull up a first voltage level at the output terminal to ground in response to a signal to accelerate leakage of a first leakage current; and a second discharge device coupled to a voltage generator circuit to pull down a second voltage level at a cell plate node of the memory cell to ground in response to the signal to accelerate leakage of a second leakage current, wherein the cell plate node is coupled to a storage node of the memory cell by a capacitor. Other embodiments may also be described and claimed.

Apparatuses, methods, and systems for increasing a speed of removal of data from a memory cell

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Portland, OR, United States of America

Shih-Lien L Lu