Advanced Semiconductor Engineering, Inc.

Xintec Corporation

Shih-Kuang Chen

Shyh-Ing Wu

Su Tao

Tsung-Hua Wu

Bai-Yao Lou

Chueh-An Hsieh

Li-Cheng Tai

Tai-Chun Huang

Chun-Hung Lin

Ho-Ming Tong

Jen-Kuang Fang

Chia-Ming Cheng

Chun-Chi Lee

Yung-Chi Lee

Yu-Chen Chou

Shin-Hua Chao

Chang-Chi Lee

Ching-Fu Horng

Hsin Kuan

Chih-Hsiang Hsu

Jiunn Chen

Jui-I Yu

Tsung-Chieh Ho

Han-Hsiang Huang

Chin-Ching Huang

Sheng-Yuan Lee

Chih-Hao Chen

Chin-Long Wu

Yuan-Ting Chang

A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.

Chip package and manufacturing method thereof

An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.

Chip package and method for forming the same

A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid.

Wafer packaging method

A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and a sealant. The distribution layer has a first surface and a second surface, and the chip is disposed on the first surface. Each internal conductor has a first terminal and a second terminal. The first terminal is disposed on the first surface. The sealant is disposed on the first surface for covering the chip and partly encapsulating the internal conductors, so that the first terminal and the second terminal of each internal conductor are exposed from the sealant. The external conductors disposed on the second surface of the distribution layer of the package portion are electrically connected to the internal conductors.

Chip package structure and method of manufacturing the same

A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.

Bumping process and structure thereof

A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.

Wafer structure with a multi-layer barrier in an UBM layer network device with power supply

In a method for manufacturing an under-bump metallurgy (UBM) layer, a plate having a plurality of openings is prepared. Then, the plate is placed on the wafer. Finally, the material of the under-bump metallurgy layer is sputtered on the wafer using the plate as a sputter mask so as to quickly form the under-bump metallurgy layer.

Method for manufacturing an under-bump metallurgy layer

A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.

Solder paste for fabricating bump

A ball grid array semiconductor package includes a substrate, a die mounted on the substrate and electrically connected to the substrate by bonding wires, a heat ring mounted on the substrate to surround the die and the bonding wires, and a heat slug mounted on the heat ring to entirely cover the die and the bonding wires thereby providing improved heat dissipation efficiency and overall electrical performance. Encapsulation material is filled into an inner space surrounded by the heat ring, heat slug and substrate to form an encapsulant for protecting the die and bonding wires. The heat ring and heat slug has at least a portion of surface area sequentially coated with a metal medium layer and an insulation layer to enhance the bonding degree between the encapsulant and the heat ring and heat slug.

Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability

Growing community of inventors

Kaohsiung, Taiwan

Shih-Kuang Chen