Integrated Device Technology, Inc.

Lam Research Corporation

Lam Research Corpporation

Shih-Ked Lee

Chuen-Der Lien

Guo-Qiang Lo

Tsengyou Syau

Wanqing Cao

Guo-Qiang (Patrick) Lo

Cheng-Chen Calvin Hsueh

Samantha SiamHwa Tan

Chu-Tsao Yen

Yang Pan

Gaolong Jin

Eric A Hudson

Sang-Yun Lee

Wenbing Yang

Jun Xue

Guo-Qiang Patrick Lo

Yiwen Fan

Karthik Subramanian Colinjivadi

Ran Lin

Mary Anne Manumpil

Brian Schorr

Gary Foley

James R Shih

Ohm-Guo Pan

Wook Choi

George Matamis

Raashina Humayun

Jon Henri

Patrick A Van Cleemput

Jeong Yeol Choi

Juwen Gao

Mario F Au

Samantha S H Tan

Long-Ching Wang

Akhil N Singhal

Yongsik Yu

Kapu Sirish Reddy

Hongyong Xue

Samantha Siamhwa Tan

Jialing Yang

Tamal Mukherjee

Matthew Scott Weimer

Pailu D Wang

Chih-Hsiang Chen

Robert B Hixson

Mohand Brouri

Eric Lee

Chanyuan Liu

Ragesh Puthenkovilakam

Francis Sloan Roberts

Kuilong Wang

Zhenjiang Yu

Yu-Lung Mao

Ching-Kai (Robert) Lin

Yingbo Jia

Timothy P Kay

Tong Zhang

Chin-Jui Hsu

Gordon Alex Macdonald

Louis Huang

Shaoqing Zhang

Xizhu Zhao

Huifeng Zheng

Todd Shroeder

Provided herein are methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate in a low pressure chamber using a dual frequency radio frequency component. Low pressure plasma enhanced chemical vapor deposition may be used to increase the etch selectivity of the AHM, permitting the use of a thinner AHM for semiconductor processing operations.

High density, modulus, and hardness amorphous carbon films at low pressure

A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.

Atomic layer etching for subtractive metal etch

Fabricating a semiconductor substrate by (a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate and (b) depositing an amorphous carbon liner onto the sidewalls of the feature. Steps (a) and optionally (b) are iterated until the vertical etch feature has reached a desired depth. With each iteration of (a), the feature is vertical etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. With each optional iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is replenished.

Carbon based depositions used for critical dimension control during high aspect ratio feature etches and for forming protective layers

A method for depositing a carbon ashable hard mask layer on a substrate includes a) arranging a substrate in a processing chamber; b) setting chamber pressure in a predetermined pressure range; c) setting a substrate temperature in a predetermined temperature range from −20° C. to 200° C.; d) supplying a gas mixture including hydrocarbon precursor and one or more other gases; and e) striking plasma by supplying RF plasma power for a first predetermined period to deposit a carbon ashable hard mask layer on the substrate.

High etch selectivity, low stress ashable carbon hard mask

Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.

Metal-containing passivation for high aspect ratio etch

A seed layer of aluminum is deposited over a wafer. A layer of photoresist material is deposited over the seed layer of aluminum. The photoresist material is patterned and developed to expose portions of the seed layer of aluminum through openings in the photoresist material. An electrochemical transformation process is performed on the wafer to electrochemically transform the portions of the seed layer of aluminum that are exposed through openings in the photoresist material into anodic aluminum oxide (AAO). The AAO includes a pattern of holes that extend through the AAO to expose areas of the top surface of the wafer beneath the seed layer of aluminum. The photoresist material is removed from the wafer. The wafer is exposed to a plasma to etch holes into the wafer at the areas of the top surface of the wafer that are exposed by the pattern of holes in the AAO.

Anodic aluminum oxide as hard mask for plasma etching

A cell library is disclosed that includes soft error resistant logic cells. The soft error resistant logic cells can be used along with memory cells and conventional logic cells to form integrated circuit designs having increased soft error resistance. A method for forming an integrated circuit device is disclosed in which a first integrated circuit design is formed using conventional logic cells. An iterative process is then performed in which some of the conventional logic cells are replaced with high soft error resistant logic cells to obtain a soft error resistant design. Each soft error resistant logic cell that replaces a corresponding conventional logic cell will have the same cell size as the cell that is replaced, producing a soft error resistant design that does not take up additional surface area on the semiconductor substrate.

Method for forming integrated circuit device using cell library with soft error resistant logic cells

A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.

Method for forming CMOS device with self-aligned contacts and region formed using salicide process

A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through the die seal. In another aspect of the present invention the die seal structure includes a die seal and a bipolar structure. In this embodiment the die seal only connects to the semiconductor substrate through the bipolar structure.

Die seal with reduced noise coupling

A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.

Binary and ternary non-volatile CAM

A self-biased electrostatic discharge (ESD) protection circuit for protecting an integrated circuit operating in a normal voltage range that includes both positive and negative voltage levels is disclosed. The self-biased ESD protection circuit includes an input connection for receiving an input voltage, a protection transistor electrically coupled to the input connection, and an electrical sink. The protection transistor is operable to provide ESD protection from the input connection to the electrical sink. The self-biased ESD protection circuit also includes a metal oxide semiconductor (MOS) biasing network electrically coupled to the input connection and the protection transistor. The MOS biasing network is operable to cause the protection transistor to remain in a non-conductive state when the input voltage is in the normal operating voltage range. Upon the occurrence of an electrostatic discharge event at the input connection, the protection circuit becomes conducting to discharge ESD current from the input connection to the electrical sink.

Self-biased electrostatic discharge protection method and circuit

The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Thin film resistor structure

Sidewall spacers are disclosed that extend on opposing sidewalls of gate stacks. The sidewall spacers have improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stackhaving a sidewall is formed over the gate dielectric layer. The gate stackcomprises a conductive layerand a hard maskoverlying the conductive layer. A lineris selectively deposited over the gate stacksuch that the lineris deposited on the hard maskat a rate lower than the rate of deposition on the conductive layer. Thus, the lineris substantially thinner on the hard maskthan on the conductive layer. A nitride spacer is formed overthe liner. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks.

Gate structures having sidewall spacers formed using selective deposition

The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.

Memory cell with reduced soft error rate

Growing community of inventors

Fremont, CA, United States of America

Shih-Ked Lee