Ememory Technology Inc.

Ememory Technologies Inc.

Shih-Jye Shen

Ching-Hsiang Hsu

Hsin-Ming Chen

Ching-Sung Yang

Ming-Chou Ho

Hai-Ming Lee

Ya-Chin King

Shih-Chen Wang

Wei-Zhe Wong

Chih-Hsun Chu

Yen-Tai Lin

Chun-Hung Lu

Kung-Hong Lee

Chrong-Jung Lin

Ching-Song Yang

Shih-Chan Huang

Ming-Chiu Ho

A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.

Method of manufacturing a read-only memory device with contacts formed therein

Read-only memory device with contacts formed therein

A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

Non-volatile memory with a stable threshold voltage on SOI substrate

An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.

Operating method of non-volatile memory

A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.

A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.

Nonvolatile single-poly memory device

A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.

Non-volatile memory and operating method thereof

A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a Psource doping region and a Pdrain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

Single-poly non-volatile memory device and its operation method

A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

Method for operating single-poly non-volatile memory device

A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

Operation method of non-volatile memory

A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.

Method for reading a single-poly single-transistor non-volatile memory cell

A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

Non-volatile memory cell

A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.

Non-volatile memory device

A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charge storage structure formed on the N-type well and between the second doped region and a third doped region of the three P-type doped regions, and a second gate formed on the charge storage structure. Data is stored in the memory cell by injecting electrons based on the channel-hot-hole induced hot-electron injection mechanism, the band-to-band tunneling induced electron injection mechanism and the Fowler-Nordheim tunneling mechanism. Data is erased from the memory cell by ejecting electrons based on the Fowler-Nordheim tunneling mechanism. Whether data is stored in the charge storage structure or not can be distinguished by read operation.

Non-volatile memory cell and method of operating the same

A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the etching of the ONO layer, a channel adjustment doping is carried out subsequently using the reverse ONO photoresist layer as an implant mask, thereby forming lightly doped regions next to the gate within the memory array area. Finally, the reverse ONO photoresist layer is then stripped.

Growing community of inventors

Hsin-Chu, Taiwan

Shih-Jye Shen