Realtek Semiconductor Inc.

Shih-Hung Wang

Ruey-Beei Wu

Ting-Ying Wu

Wen-Shan Wang

Gerchih Chou

Chun-Ming Huang

Ming-Chung Huang

Shen-Kuo Huang

Hsin-Chan Hsieh

Yu-Cong Wang

Han-Yun Tsai

An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Electronic device test method and test device

A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Power line structure

An electromagnetic band gap structure apparatus includes a first conducting layer having at least one first slot. Each of the at least one slot is arranged with a planar conductor unit, and the each planar conductor unit is coupled to a first via. The electromagnetic band gap structure apparatus further includes a second conducting layer in parallel with the first conducting layer. The second conducting layer has a second slot. The second slot is arranged with at least one planar transmission line unit. The each of the at least one planar transmission line unit is coupled to the first conducting layer through a second via, and the each first via is coupled to the second conducting layer.

Electromagnetic band gap structure apparatus

A 3D electromagnetic bandgap circuit includes: a dielectric layer having a first surface and an opposing second surface; a spiral element positioned on the first surface; a first surrounding element positioned on the first surface and surrounding the spiral element, but does not touch with the spiral element; a plane element positioned on the second surface and including a notch; a second surrounding element positioned on the second surface and surrounding the plane element, but does not touch with the plane element, wherein the second surrounding element further includes a protruding portion extending toward the notch; a first via passing through the dielectric layer, the spiral element, and the protruding portion; a second via passing through the dielectric layer, the plane element, and the first surrounding element; and a third via passing through the dielectric layer, the plane element, and the first surrounding element.

3D electromagnetic bandgap circuit

A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Growing community of inventors

Miaoli County, Taiwan

Shih-Hung Wang