Mediatek Corporation

Mediatek Incorporation

Shih-Hung Lin

Yung-Chang Chang

Chi-Cheng Ju

Ching-Chieh Wang

Chih-Chien Huang

Tien-Chang Chang

Te-Chi Hsiao

Chao-Chun Tu

Wei-Jen Chen

Yao-Huang Hsieh

An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.

Decoding method and decoding apparatus for using parallel processing scheme to decode pictures in different bitstreams after required decoded data derived from decoding preceding picture(s) is ready

An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Integrated circuit chip with reduced IR drop

An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein The first bitstream contains pictures of a first view for a 3D video presentation, the second bitstream contains pictures of a second view for the 3D video presentation, and a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.

A microprocessor system contains a read-only memory (ROM) for storing programs or firmware. Retrieval and execution of program code is controlled by a microprocessor address bus. Erroneous data in the ROM can be corrected by address comparison and translation. Trap, region, and patch tables are provided to store addresses, regions, and translated addresses. An address issued by the microprocessor is stored in the trap and region tables can be translated for selecting another programmable device, such as a SRAM or DRAM, other than the original ROM. Thus, erroneous code in the ROM can be corrected, inserted, or replaced.

Growing community of inventors

Hsinchu, Taiwan

Shih-Hung Lin