Macronix International Co., Ltd.

International Business Machines Corporation

United Microelectronics Corp.

Shih-Hung Chen

Hang-Ting Lue

Yen-Hao Shih

Hsiang-Lan Lung

Hsiang Lan Lung

Yi-Chou Chen

Erh-Kun Lai

Kuang-Yeu Hsieh

Kuang Yeu Hsieh

Yi-Hsuan Hsiao

Rich Liu

Chung H Lam

Chun-Hsiung Hung

Alejandro Gabriel Schrott

Ming-Hsiu Lee

Matthew Joseph Breitwisch

Eric Andrew Joseph

Min Yang

ChiaHua Ho

Chin-Cheng Yang

Michael F Lofaro

Hong-Ji Lee

Chieh-Fang Chen

Lo-Yueh Lin

Teng-Hao Yeh

Stephen Mark Rossnagel

Chih-Wei Hu

Wei-Chih Chien

Hsuan-Hsu Chen

Chih-Chang Hsieh

Tzu-Hsiang Su

Yi-Tyng Wu

Yan-Ru Chen

Cheng-Yuan Wang

I-Jen Huang

Chien-hua Tsai

Feng-Nien Tsai

Chih-Hung Cheng

Huai-Hsuan Tsai

Tian-Jue Hong

A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.

Memory device

A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.

Three-dimensional semiconductor device

A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Memory device and data searching method thereof

A chip includes a substrate and a plurality of functional units on the substrate, in which each of the functional units has its own set of pads. The functional units are physically connected and there is no scribe line passes through the chip. A semiconductor structure having the chip is also disclosed.

Chip having multiple functional units and semiconductor structure using the same

A memory device and a manufacturing method for the same are provided. The memory device includes a stacked body structure and a staircase structure. The stacked body structure includes a first sub-stacked body structure and a second sub-stacked body structure. The staircase structure is electrically connected to the stacked body structure. The staircase structure includes a first sub-staircase structure and a second sub-staircase structure. Each of the first sub-staircase structure and the second sub-staircase structure includes a first staircase portion and a second staircase portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first staircase portion of the first sub-staircase structure and the first staircase portion of the second sub-staircase structure.

Memory device and manufacturing method for the same

A method for generating a classification model using a training data set. An iterative procedure for training an ANN model, in which an iteration includes selecting a small sample of training data from a source of training data, training the model using the sample, using the model in inference mode over a larger sample of the training data, and reviewing the results of the inferencing. The results can be evaluated to determine whether the model is satisfactory, and if it does not meet specified criteria, then cycles of sampling, training, inferencing and reviewing results (STIR cycles) are repeated in an iterative process until the criteria are met. A classification engine trained as described herein is provided.

Classification model training using diverse training source and inference engine using same

A three-way switch array structure including N first connectors, M second connectors, N&#xd7;M third connectors and N&#xd7;M three-way switches is provided, each three-way switch has a first terminal, a second terminal, a third terminal, a first switch and a second switch. Each of first terminals is disposed on one of the first connectors, each of second terminals is disposed on one of the second connectors, and each of third terminals is disposed on one of the third connectors, the first switch is disposed between the first terminal and the third terminal, and the second switch is disposed between the second terminal and the third terminal, wherein N and M are positive integers greater than or equal to 1.

Three-way switch array structure and switch array substrate based on NVM

A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

Resistor circuit, artificial intelligence chip and method for manufacturing the same

A technology for cleaning a training data set for a neural network using dirty training data starts by accessing a labeled training data set that includes relatively dirty labeled data elements. The labeled training data set is divided into a first subset A and a second subset B. The procedure includes cycling between the subsets A and B, including producing refined model-filtered subsets of subsets A and B to provide a cleaned data set. Each refined model-filtered subset can have improved cleanliness and increased numbers of elements.

Data set cleaning for artificial neural network training

A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.

Neuromorphic computing device

A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

Multilayer structure and method for fabricating the same

A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

3D NAND word line connection structure

3D NAND world line connection structure

Growing community of inventors

Hsinchu County, Taiwan

Shih-Hung Chen