United Microelectronics Corp.

Mediatek Corporation

Mediatek Incorporation

United Silicon Incorporated

Shih-Huang Huang

Hsin-Pang Lu

Rei-Fu Huang

Juei-Lung Chen

Jui-Lung Chen

Shu-Lin Lai

Shu-Hsuan Lin

The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

Differential sensing circuit with dynamic voltage reference for single-ended bit line memory

A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

Sense amplifier circuits

A write assist circuit capable of writing data to a memory cell with a bit line and a bit line bar is provided. The write assist circuit includes a clamping circuit, and first and second sense amplifiers. The clamping circuit is coupled to first and second nodes to prevent the voltage of the first and second nodes from being lower than a data-retention voltage. The first and second nodes are supplied with first and second voltage sources. The first and second sense amplifier are utilized to detect the voltage of the bit line or the bit line bar, amplify the voltage and pull down the voltage of one of the first or second node according to the data while the voltage of the other one of the first or second node is kept at a power supply voltage level.

Write assist circuit and memory cell

A word line control circuit includes a first PMOS transistor having a gate coupled to a first selection signal; a first NMOS transistor, coupled between a second node and a second voltage terminal, having a gate coupled to an inverted first selection signal, wherein the inverted first selection signal is obtained by inverting the first selection signal; and a plurality of word line drivers, at least one of the word line drivers comprising a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first voltage terminal, a negative power terminal of the first inverter is coupled to the second node, a positive power terminal of the second inverter is coupled to the first node, and a negative power terminal of the second inverter is coupled to the second voltage terminal.

Memory circuit and word line control circuit

The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.

Memory output circuit

The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

The disclosure relates to a voltage converter, converting a first signal of a first voltage to output a second signal of a second voltage. A level shifter receives the first signal to generate the second signal. An isolation circuit is coupled to the output of the level shifter, passing the second signal out. When the input of voltage converter is floated, the isolation circuit stops passing the second signal as the output, instead, the isolation circuit outputs a substitution signal having a predetermined voltage level irrelevant to the input of the level shifter.

Voltage converter with auto-isolation function

A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining a signal on the first data line at a voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. A third pre-charging module is electrically connected to the second data line for pre-charging the second data line.

Sensing circuit for single bit-line semiconductor memory device

A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

Delay lock circuit using bisection algorithm and related method

A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit contains a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining the signal on the first data line at a high voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. Finally, a third pre-charging module is electrically connected to the second data line for pre-charging the second data line.

A pre-charge and sense out circuit for differential type ROM. The ROM is capable of connecting to either a first bit line or a second bit line. The pre-charge and sense out circuit contains a pre-charging module electrically connected to the first and the second bit lines, for pre-charging the first and the second bit lines; a selecting module electrically connected to the first bit line, the second bit line, a first data line, and a second data line, for transmitting data according to a first control signal; a charge sharing module electrically connected to the first and the second data lines, for sharing electrical charges to the first and the second data lines; and a sensing module electrically connected to the first and the second data lines, for sensing signals on the first and the second data lines so as to generate an output signal.

Pre-charge and sense-out circuit for differential type ROM

A digital delay phase locked loop, to quickly perform the phase lock on an input clock signal. The digital delay phase locked circuit has a delay apparatus, a buffer, a phase comparator, an adder-register, a clock divider and a demultiplexer. After a delay operation performed on the input clock signal by the delay apparatus, the phase locked clock signal is output via the buffer. The above two signals are then compared with each other using the phase comparator to output a comparison signal to the adder-register for addition/subtraction delay. Being controlled by the clock divider, the objective of fast phase lock is achieved by the addition/subtraction operation of the demultiplexer.

Digital delay phase locked loop

A selective memory refresh circuit for refreshing a memory cell array. The memory cell array has a plurality of word lines connected to a plurality of word line selection circuits for determining if a particular word line needs to be refresh during a refresh cycle. Each word line refresh selection circuit further has a word line address latching device for receiving a word line pre-decode signal, a release signal, a triggering signal and outputting a word line latching signal and a word line refresh compare circuit for receiving the word line pre-decode signal and the word line latching signal and transmitting the result of comparison to a word line driver. When the word line latching signal is at a high level, memory cells attached to the word line are refreshed. On the contrary, when the word line latching signal is at a low level, memory refresh for that word line is skipped.

Selective memory refresh circuit and method

A memory device has an output buffer. The output buffer is electrically connected to a data output port of a sense amplifier of the memory device for amplifying an output signal from the data output port. The output buffer has a detector for producing a control signal according to the output signal from the data output port, and an amplifier for amplifying the output signal from the data output port. The amplifier has an input port electrically connected to the data output port for accepting the output signal from the data output port, and a control terminal electrically connected to the output terminal of the detector for accepting the control signal from the detector to control operations of the amplifier. When the detector produces the control signal and transmits the control signal to the control terminal of the amplifier, the amplifier begins amplifying the output signal transmitted from the data output port to the input port of the amplifier.

Growing community of inventors

Hsin-Chu, Taiwan

Shih-Huang Huang