Industrial Technology Research Institute

Chung Yuan Christian University

Tsinghua University

Springsoft USA, Inc.

Shih-Hsu Huang

Yow-Tyng Nieh

Chia-Ming Chang

Yeong-Jar Chang

Sheng-Yu Hsu

Shih-Chieh Chang

Hsin-Po Wang

Yu-Sheng Lu

Yuan-Kai Ho

Jia-Zong Lin

Che-Wei Tung

Chung-Han Chou

A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N&#x2212;1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N&#x2212;1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.

Multiplication accumulating device and method thereof

A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Clock tree in circuit having a power-mode control circuit to determine a first delay time and a second delay time

Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

Methods and systems for reducing clock skew in a gated clock tree

We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Opposite-phase scheme for peak current reduction

A method for controlling a peak current is provided. The method first uses a plurality of registers to encode a plurality of states of a circuit and generates an original state code. Then, the original state code is re-encoded to reduce the difference between the sum of charging current of the charged registers and the sum of discharging current of the discharged registers while the registers are switched among the charging/discharging states. Finally, a standard technology library is read and logic circuit synthesis is performed for the re-encoded state codes.

Method for controlling peak current of a circuit having a plurality of registers

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Hsinchu County, Taiwan

Shih-Hsu Huang