Etron Technology, Inc.

National Yang Ming Chiao Tung University

Shih-Hsing Wang

Der-Min Yuan

Chung-Chih Hung

Tah-Kang Joseph Ting

Hong-Jie Chen

Chun Shiah

Yen-An Chang

Bor-Doou Rong

Yi-Hao Chang

Lien-Sheng Yang

Te-Yi Yu

Chun-Ching Hsia

Ming-Cheng Liang

Kuo-Cheng Ting

Kuo-Hua Lee

Wen-Tung Yang

Chih-Ming Cheng

Min-Chih Chang

Che-Chun Ou Yang

A comparator circuit with low power consumption and low kickback noise includes a first dynamic comparator and a second dynamic comparator. The first dynamic comparator is a pre-amplifier for the second dynamic comparator. An enable switch which is connected to the first dynamic comparator has a control terminal connected to a resistance device. The resistance device and the enable switch form a RC delay circuit to reduce the kickback noise of the comparator circuit. Since the comparator circuit is composed of dynamic comparators, the power consumption of the comparator circuit is lower.

Comparator circuit with low power consumption and low kickback noise

A two-step switching method of circuit switch can be used in a charge pump circuit of a phase locked loop circuit. In the method, a first type switch and a second type switch which have the same sizes and are opposite in type, are provided. The first type switch and second type switch continuously receive an input current, and the input current is kept at a low current state in a first stage before the first type switch and the second type switch are turned on. In a second stage, the first type switch and the second type switch are turned on, the input current is gradually adjusted to a target current state, and the input current of the target current state is gradually supplied to an external circuit. The present method can reduce noise generated by the external circuit, reduce power loss, and offset charge injection.

Two-step switching method for a circuit switch

A charge pump circuit and a phase-locked loop (PLL) system using the same are provided. The charge pump circuit includes an upper current source, a lower current source and a plurality of switches. The switches are turned on or off by an error signal to increase or decrease the control voltage of the voltage-controlled oscillator (VCO) and further control the frequency of the output signal of the VCO. When the reference frequency signal matches with the divided frequency signal from the VCO, the upper current source and the lower current source are bypassed to decrease the voltage across the MOSFET, thereby minimizes the influence of the leakage current on the control voltage of VCO. In this way, the output jitter can be reduced due to smaller magnitude of peak-to-peak voltage on the control voltage of VCO in the PLL system caused by the leakage current of the MOSFET.

Charge pump circuit and phase locked loop system using the same

A method for improving test coverage of pads of a chip, where the chip includes a control unit, a plurality of pads, and a storage unit, and the storage unit includes a plurality of blocks, includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.

Chip capable of improving test coverage of pads and related method thereof

An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.

Input receiver and operation method thereof

By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.

Method of detecting connection defects of memory and memory capable of detecting connection defects thereof

A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.

Device for generating a test pattern of a memory chip and method thereof

A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.

Memory having a disabling circuit and method for disabling the memory

Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory.

Testing system and method thereof

This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.

System in package integrated circuit with self-generating reference voltage

A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.

Data detecting apparatus and methods thereof

Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from '1' to '0' or vice versa data lines are inverted accordingly during WRITE operation.

Data flow scheme for low power DRAM

The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module.

Memory row architecture having memory row redundancy repair function

A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

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Hsinchu, Taiwan

Shih-Hsing Wang