Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Optoelectronic Technology, Inc.

Shih-Hsiang Lo

Ru-Gun Liu

Hsu-Ting Huang

Chin-Hsiang Lin

Chih-Ming Lai

Jue-Chin Yu

Fu An Tien

Tung-Chin Wu

Hsin-Ting Hung

Chuang-Yu Hsieh

Hao-Hsiang Hsieh

A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

Method of manufacturing integrated circuit

The present disclosure provides an optical packaging structure and a backlight module with the optical packaging structure. The optical packaging structure includes a light-emitting chip, a packaging layer, a fluorescent layer, a lens structure, and a reflecting layer. The light-emitting chip includes a light-emitting surface, a connecting surface, and a side surface. The packaging layer covers the light-emitting surface and the first side surface. The connecting surface is exposed from the packaging layer. The fluorescent layer is disposed on the packaging layer, and covers on the light-emitting surface and the first side surface. The lens structure is disposed on a top surface of the fluorescent layer. A surface of the lens structure is recessed towards the light-emitting chip to form a curved surface. The reflecting layer is disposed on the curved surface.

Optical packaging structure and backlight module having the same

Method of mask data synthesis and mask making

A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

Method for mask data synthesis with wafer target adjustment

In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

Lithography simulation method

Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

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Hsinchu, Taiwan

Shih-Hsiang Lo