Taiwan Semiconductor Manufacturing Comp. Ltd.

Digwise Technology Corporation, Ltd

Global Unichip Corporation

Tpk Advanced Solutions Inc.

Shih-Hao Chen

Mu-Tsang Lin

Chih-Han Lin

Che-Cheng Chang

Jr-Jung Lin

Tung-Wen Cheng

Wei-Yang Lo

Yung Jung Chang

Wen-Pin Hsieh

Chih-Wen Yang

Kuo-Lung Fang

Yung-Jung Chang

Shih-Ping Hong

Chen-Hsiang Lu

Jun-Rong Chen

Jingjie Wu

Tai-Cheng Lee

Chien-Yu Wang

Hung-Bin Lin

You-Zhi She

Jun-Ping Yang

Xiao-Xia You

Chiou-Bang Chen

Qi-Bin Liu

Qi-Jun Zheng

Jun-Jie Zheng

Ping-Chung Lee

Heng-Jui Liu

A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Device and method for integrated circuit assistance design, and method for constructing electrical performance gradient model

A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.

Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features

A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Setup time and hold time detection system and detection method

An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.

Plasma etcher edge ring with a chamfer geometry and impedance design

A clock and data recovery circuit includes a first sampling phase detector and filter circuitry, a frequency detector circuit, a current source circuit, a band controller circuit, and a voltage controlled oscillator. The first sampling phase detector and filter circuitry generates a first voltage according to a pair of data and a first set of clock signals. The frequency detector circuit generates an up control signal and a down control signal according to the pair of data and the first set of clock signals. The current source circuit generates the first voltage according to the up control signal and the down control signal. The band controller circuit generates a band control signal according to the first voltage. The voltage controlled oscillator adjusts the first set of clock signals according to the band control signal and the first voltage.

Clock and data recovery circuit

A memory device including a voltage boosting circuit, a switching circuit and a word line driving circuit is provided. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is turned on or cut-off according to a first mode selection signal. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.

Memory device with voltage boosting circuit

A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.

Semiconductor apparatus

A touch module includes a touch panel unit, a conductive adhesive layer and a circuit board. The touch panel unit includes a substrate, a touch sensing structure disposed on the substrate, a signal transmitting structure disposed on the substrate and electrically connected to the touch sensing structure, and a protection layer covering a part of a surface of the signal transmitting structure. The protection layer and the substrate are disposed at two opposite sides of the signal transmitting structure. The conductive adhesive layer has a main portion which covers a region of the signal transmitting structure on which the protection layer is not disposed, and a cover portion which extends from the main portion and covers the protection layer. The circuit board is disposed on the conductive adhesive layer, and the circuit board and the signal transmitting structure are disposed at two opposite sides of the conductive adhesive layer.

Touch module and method for manufacturing the same

A transistor includes a semiconductive fin having a channel portion, a gate stack over the channel portion of the semiconductive fin, source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, and a sidewall structure extending along sidewalls of a body portion of the source structure. The source structure has a curved top, and the source structure has a top portion protruding over a top of the sidewall structure.

Semiconductor device

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer. The semiconductor device further includes a second dielectric layer vertically between the first dielectric layer and the gate spacer, wherein the first and second dielectric layers include different materials, and wherein the second dielectric layer is in physical contact with the gate spacer and the first dielectric layer.

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.

A method for manufacturing a semiconductor device includes forming a gate stack over a semiconductor fin such that the gate stack exposes the semiconductor fin. The semiconductor fin exposed by the gate stack is recessed. An epitaxy structure is epitaxially grown on a recessed portion of the semiconductor fin, and the epitaxy structure is etched such that the epitaxy structure has a curved top.

Method of manufacturing semiconductor device

A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A portion of the semiconductor fin is protruded from the substrate. The gate stack is disposed over the portion of the semiconductor fin protruded from the substrate. The epitaxy structure is disposed on the substrate and adjacent to the gate stack. The epitaxy structure has a top surface facing away the substrate, and the top surface has at least one curved portion having a radius of curvature ranging from about 5 nm to about 20 nm.

A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.

Growing community of inventors

Hsinchu County, Taiwan

Shih-Hao Chen