Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Guo Shen

Der-Chyang Yeh

An-Jhih Su

Yu-Hung Lin

Chia-Nan Yuan

Wen-Chuan Chiang

Ming-Shih Yeh

Chien-Chung Wang

Huey-Chi Chu

Wei-Min Tseng

Chen-Hua Douglas Yu

Ming Shih Yeh

Shao-Yu Chou

Ren-Fen Tsui

Po-Hung Chen

Dian-Sheg Yu

Liang Chuan Chang

Bai-Mei Chang

Wei-Fen Pai

In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

Semiconductor device and method

A method of manufacturing a semiconductor device includes the following steps. A semiconductor substrate is provided. A plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. At least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. A plurality of conductive connectors are formed to electrically connect to the second conductive features. The semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.

Methods of manufacturing semiconductor devices

A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.

Semiconductor devices

A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

Semiconductor devices and methods of manufacturing the same

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.

Electrical fuse bit cell and mask set

The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.

MIM capacitor structure

The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.

The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.

Growing community of inventors

New Taipei, Taiwan

Shih-Guo Shen