Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Feng Huang

Kuo-Su Huang

Chih-Feng Huang

Yi-Sin Wang

Chi-Hsu Chiu

Arjit Ashok

The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

Apparatus and method for measuring performance of memory array

A pattern for monitoring epitaxial layer washout is disclosed. The pattern includes first and second sub-patterns. The first sub-pattern has a shape and defines one or more minimum dimensions. Obfuscation of the first sub-pattern means that epitaxial washout has occurred at least for dimensions equal to or less than the minimum dimensions. The second sub-pattern has the same shape of the first sub-pattern, but defines one or more maximum dimensions. Obfuscation of the second sub-pattern means that epitaxial washout has occurred for dimensions equal to or less than the maximum dimensions. The sub-patterns can include a pair of separated features, such as a pair of interlocking but separated L-shaped features, the separation of which defines the dimensions of the sub-patterns.

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Taoyuan, Taiwan

Shih-Feng Huang