Northrop Grumman Systems Corporation

Shih-En Shih

Philip W Hon

Dah-Weih Duan

Arun K Bhattacharyya

Roger S Tsai

Xianglin Zeng

William Roland Deal

Kevin M Leong

Gregory P Krishmar-Junker

Jose G Padilla

Loc B Chau

David I Stones

Ben Gorospe

A terahertz waveguide bandpass filter block assembly including a waveguide iris filter, a pedestal block having a pedestal channel including a first one-half portion of the iris filter, and a cover block having a cover channel including a second one-half portion of the iris filter, where the first and second one-half portions combine to define the iris filter having a plurality of poles when the pedestal block and the cover block are secured together. The assembly also includes first and second ribbon strips positioned on opposing sides and adjacent to the iris filter between the pedestal block and the cover block, where a compression force between the pedestal block and the cover block compresses the first and second ribbon strips and sets an 'a' dimension of the iris filter to tune the filter to a frequency band of interest.

Terahertz filter tuning

A flared feed horn including a plurality of signal lines deposited on a bottom surface of a substrate and forming part of a TEsum mode launcher, a ground plane deposited a top surface of the substrate, and an outer conductor electrically coupled to the ground plane and having an internal chamber, where the conductor includes a flared portion and a cylindrical portion. The outer conductor includes an opening opposite to the substrate defining an aperture of the feed horn. The feed horn also includes an embedded conductor positioned within the chamber and being coaxial with the outer conductor, where the embedded conductor is in electrical contact with the plurality of signal lines. The feed horn also includes a TEdifference mode launcher electrically coupled to the outer conductor proximate the aperture.

Compact wide band, flared horn antenna with launchers for generating circular polarized sum and difference patterns

A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

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Torrance, CA, United States of America

Shih-En Shih