Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Chyi Wong

Jian-Hsing Lee

Kuo-Reay Peng

An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P&plus; diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N&plus; diffusion) next to the it. The drain and the P&plus; diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P&plus; diffusion) is located on either side of each source (N&plus; diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P&plus; diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

Low capacitance ESD protection device

An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P&plus; diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N&plus; diffusion) next to the it. The drain and the P&plus; diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P&plus; diffusion is located on either side of each source (N&plus; diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P&plus; diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

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Taichang, Taiwan

Shih-Chyi Wong