Novatek Microelectronics Corp.

I-shou University

Shih-Chun Lin

Yung-Cheng Lin

Mu-Jung Chen

Ren-Hong Luo

Ming-Hung Chien

Shu-Chin Chuang

Yu-Jung Huang

Chung-Long Pan

Mei-Hui Guo

A signal transmitter includes a plurality of driver slices. Each of the driver slices includes a driving circuit, a plurality of first transistors, and a plurality of second transistors. The driving circuit receives an input signal and outputting an output signal. The first transistors provide a first impedance according to signals on gate terminals of the first transistors. The second transistors provide a second impedance according to signals on gate terminals of the second transistors. Each of the gate terminals of the first transistors and the second transistors is selectively coupled to a bias voltage which controls the corresponding first transistor or second transistor to operate in a triode region, or coupled to a predetermined voltage which controls the corresponding first transistor or second transistor to behave as a switch.

Signal transmitter and impedance adjustment method thereof

A voltage mode transmitter includes a first output terminal, a second output terminal, and a plurality switch-resistor units between the first output terminal and a first voltage source, between the second output terminal and the first voltage source, between the first output terminal and a second voltage source, and between the second output terminal and the second voltage source. Each switch-resistor unit includes a switch and a resistor connected in series. The switches of the switch-resistor units are controlled such that a common-mode voltage of a differential signal outputted at the first and second output terminals deviates from an average of voltages provided by the first and second voltage sources.

Voltage mode transmitter

A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.

Voltage regulator and method applied thereto

A defect detection method for a 3D chip and a system using the same are provided. The method includes: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a 3D chip; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that a Through Silicon Via of a single die 3D chip or a stacked die 3D chip has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.

Defect detection method for 3D chip and system using the same

The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Growing community of inventors

Kaohsiung, Taiwan

Shih-Chun Lin