Himax Technologies, Inc.

Shih-Chun Lin

Wen-Teng Fan

Chan-Fei Lin

A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

Clock data recovery circuit

A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2sub-phases, so that the multi-phase clock generator has 2phase selections.

Multi-phase clock generator

The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.

Timing controller and clock signal detection circuit thereof

A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.

Phase selector

A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).

Spread-spectrum generator

A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit.

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Tainan County, Taiwan

Shih-Chun Lin