Macronix International Co., Ltd.

Shih-Chou Juan

Nai-Ping Kuo

Kuan-Chieh Wang

Shunli Cheng

Shun-Li Cheng

Han-Sung Chen

Shuo-Nan Hung

Chun-Lien Su

Chun Hsiung Hung

Yi-Chun Liu

Chien-Hsin Liu

Hsin Yi Ho

Lung Yi Kuo

Wei-Yan Jang

Jia-Xing Lin

Hung-Yi Chiang

Shao-Yu Wang

Min-Zhi Ji

Systems, devices, methods, and circuits for managing power supply in semiconductor devices are provided. The semiconductor devices can include 3D NAND flash memory devices with high capacity and/or high performance. In one aspect, a semiconductor device includes: a voltage pump, a pump switch circuit configured to be coupled to the voltage pump, and an interface including a voltage pin coupled to the pump switch circuit. The voltage pump has an input, an output, and a series of pump stages coupled between the input and the output. The pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at the output of the voltage pump.

Managing power supply in semiconductor devices

A scan chain circuit and an operation method thereof are provided. The scan chain circuit includes a plurality of scan chain units. Each of the scan chain units includes a plurality of input scan flip-flop (SFF) and a comparison circuit. After a plurality of input bit values are operated by a logic circuit, a plurality of actual operation result bit values are obtained. The comparison circuit is used to receive the actual operation result bit values and a plurality of predetermined operation result bit values. Each of the predetermined operation result bit values is each of a plurality of predetermined operation results after each of the input bit values is operated by the logic circuit. The comparison circuit compares the actual operation bit values and the predetermined operation result bit values, and then outputs a bits comparison result bit value.

Scan chain circuit and operation method thereof

A control method, for controlling a reading operation of a memory device, includes the following steps. A toggle signal is provided to the memory device, and the toggle signal has a toggle frequency. A reading operation of a page of the memory device is performed according to the toggle signal, wherein the page includes a plurality of chunks. The toggle frequency is set as a target toggle frequency, and the reading operation of a first chunk of the page is performed according to the target toggle frequency, so as to receive a data signal of the memory device. After the reading operation of the first chunk is completed, the toggle frequency is selectively adjusted to perform the reading operation of a second chunk after the first chunk according to a stable state of the data signal and the data strobe signal.

Control method for reading operation of memory device

A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Memory device and management method thereof

Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.

Managing synchronous data transfer

A system includes a semiconductor device configured to store data and a controller communicatively coupled to the semiconductor device. The semiconductor device and the controller are configured to; in response to determining that particular data stored in the semiconductor device satisfies a reliability condition, obtain first readout data by reading the particular data at a first read voltage, and obtain second readout data by reading the particular data at a second read voltage. The second read voltage is different from the first read voltage. The semiconductor device and the controller are configured to compare the first readout data and the second readout data and obtain a comparison result; and, based on the comparison result, determine whether to perform an error correction process on the particular data.

Managing data reliability in semiconductor devices

Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Managing error correction coding in memory systems

A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

Solid state disk, data transmitting method and intermediary controller to support reduced SSD controller pad count

Method and apparatus for improving continuous read operations with expanded serial interface are provided. In one aspect, a device comprises: a memory configured to store data; a buffer configured to receive data from outside of the device and transfer the received data to the memory; a plurality of input pins configured to be coupled to an expanded serial peripheral interface (xSPI); and a processor configured to: select a slave device, through the xSPI, from a plurality of slave devices, send instruction data to the slave device for data reading, receive data, through the xSPI, from the selected slave device, and receive a signal on a data strobe line of the xSPI and determine data reading operations based on the received signal.

Methods and apparatus for improving SPI continuous read

A memory system includes a first flash memory, a second flash memory and a controller. The first flash memory includes a memory array divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory and configured to: control the second flash memory to record an address of a particular page in the first flash memory before programming the particular page; and control the second flash memory to record a program status of the particular page after the particular page has been programed.

Memory system and operating method thereof

A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.

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Taoyuan, Taiwan

Shih-Chou Juan