Acer Inc.

National Sun Yat-sen University of Kaohsiung

Shih-Ching Chen

Ting-Chang Chang

Fu-Yen Jian

Te-Chih Chen

Yong-En Syu

Po-Chun Yang

Yu-Shih Lin

A resistance random access memory element includes a first electrode, an insulating layer, a diffusing metal layer, and a second electrode superimposed in sequence. The insulating layer includes a plurality of pointed electrodes. A method for making a resistance random access memory element includes growing and forming an insulating layer on a surface of a first electrode. A diffusing metal layer is formed on a surface of the insulating layer. A second electrode is mounted on a surface of the diffusing metal layer. A negative pole and a positive pole of a driving voltage are connected with the first and second electrodes, respectively. The diffusing metal in the diffusing metal layer is oxidized into metal ions by the driving voltage. The metal ions are driven into the insulating layer and form a plurality of pointed electrodes after reduction.

Resistance random access memory element and method for making the same

There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.

Method for enabling a SONOS transistor to be used as both a switch and a memory

A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.

Operation method of memory device

A method for programming a nonvolatile memory includes applying at least a voltage to a source or a drain, so as to inject carriers of the source or drain into a substrate; applying a third voltage to a gate or the substrate, so that the carriers which are in the substrate having enough energy can surmount an oxide layer to reach a charge storage device.

Growing community of inventors

Xinzhuang, Taiwan

Shih-Ching Chen