United Microelectronics Corp.

Texas Instruments Corporation

Shih-Chin Lin

Ming-Jui Chen

Chen-Hsien Hsu

Kuei-Chun Hung

Jerry Che Jen Hu

Charlie Han

Pien Chien

Ya-Nan Mou

Yu-Yee Liow

Hsin-Wen Chen

Yuan-Hui Chen

Po-Hua Chen

Wen-Hong Hsu

Chi-Chang Shuai

Chien-Te Feng

Yen-Hsueh Huang

Pei-Geng Ma

A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

Semiconductor integrated circuit layout structure

A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.

Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch

An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Integrated circuit and signal monitoring method thereof

A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Memory cell and memory cell array using the same

In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.

Hidden refresh method and operating method for pseudo SRAM

An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads.

Integrated circuit device having die bonded to the polymer side of a polymer substrate

A static random access memory (SRAM) has a plurality of SRAM cells, a first switch unit, a second switch unit, and a capacitor. During read/write operations of the SRAM cells, the first switch unit and the second switch unit are turned on so that two power terminals of the SRAM cells respectively electrically connect to Vand Vand that the capacitor electrically connects between Vand V. When the SRAM cells are not accessed, the first switch unit and the second switch unit are turned off and the capacitor keeps a voltage gap between the two power terminals of the SRAM cells greater than a predetermined value.

Low leakage current static random access memory

In accordance with the present invention, a method is provided for testing dynamic random access memory under wafer-level-burn-in that substantially can overcome the disadvantage of requiring at a manufacturing period and which even further increases with the increase of the memory capacity being expanded. In the embodiment, first of all, there are pluralities of word lines that are arranged in parallel. Generally word line driver means respectively driving the word lines and concludes word line test means for receiving a test signal, and further for producing an output signal. The layout of input bit-line to bit-line can be cross-arranged. Thus, the main feature of the present invention is mentioned that voltage for bit-line can be divided as even-numbered voltage and odd-numbered voltage for cross toggling. Especially, all of the tests can be carried out in the fabrication period of a semiconductor factory. Also, the semiconductor memory device of this invention overcomes the above-identified problem and numerous other disadvantages and deficiencies of the conventional technology.

Method for testing dynamic random access memory under wafer-level-burn-in

A circuit is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this circuit, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

Circuit for burn-in operation on a wafer of memory devices

A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

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Hsinchu County, Taiwan

Shih-Chin Lin