Realtek Semiconductor Inc.

Industrial Technology Research Institute

Fih (Hong Kong) Limited

Richtek Technology Corporation

Tsinghua University

Quanta Computer Incorporated

Shih-Chieh Lin

Sheng-Lin Lin

Yu-Wen Hsu

Chao-Ta Huang

Chung-Yuan Su

Ta-Hua Lai

Chun-Yi Kuo

Yu-Hsin Lin

Hao-Ying Chang

Wei-Yu Chien

Chia-Yu Wu

Lung-Tai Chen

Cheng-Hung Ko

Jung-Huang Liao

Chiung-Cheng Lo

Chin-Hung Ma

Li-Wei Deng

Yu-Hsiang Lo

A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.

Circuit for testing memories

A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

Testing system and testing method

The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Memory device, memory test circuit and memory test method thereof having repair information maintaining mechanism

A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Circuit for testing memory

The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

Circuit and associated chip

A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Memory device test circuit and memory device test method

A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Test system

A dual membrane restrictor adapted to be connected to an oil supplying device, a loading device, and a recycling device is provided. The dual membrane restrictor includes a casing and first and second membranes. The casing has a first channel connected to the oil supplying device, first and second chambers, a second channel connected to the loading device, and a third channel connected to the recycling device. The first membrane is disposed in the first chamber divided into first upper and lower chambers by the first membrane. The first channel is connected to the first upper chamber. The second membrane is disposed in the second chamber divided into second upper and lower chambers by the second membrane. The second upper chamber is connected to the first lower chamber and the second channel. The second lower chamber is connected to the second channel and the third channel.

Dual membrane restrictor

A hydrostatic bearing assembly including a bearing and two membrane throttles is provided. The bearing is adapted to be movably disposed on a slide rail and includes two sub-bearing portions that are disposed opposite to each other on two opposite sides of the slide rail. The two membrane throttles are adapted to be connected to a pump. The pump is adapted to supply a fluid through the two membrane throttles to flow between the two sub-bearing portions and the slide rail, and each of the membrane throttles includes a casing and a throttling membrane piece. At least one of the casing and the corresponding sub-bearing portion includes a chamber, an inlet and an outlet communicating with the chamber, and an outlet surface, wherein the pump is adapted to be connected to the inlet, and the slide rail is adapted to be disposed adjacent to the outlet. The throttling membrane piece is being positioned in the chamber covers on the outlet surface.

Hydrostatic bearing assembly

A method for power management by a rack management controller (RMC) of a server rack includes collecting power consumption data from a first baseboard management controller (BMC) of a first server in the server rack and sending the power consumption data to a management server. The RMC receives power requirements from the management server and determines a power setting based on the power consumption data and the power requirements. The RMC requests the first BMC to limit power consumption of the first server according to the power setting.

Server rack power management

A membrane restrictor adapted to be connected to a pump and a bearing is provided. The pump is adapted to supply fluid to a location between the bearing and the rail through the membrane. The bearing is adapted to be disposed on a rail. The membrane restrictor includes a casing and a membrane. The casing has a chamber, an inlet and an outlet communicating with each other through the chamber, and a restricting plane. The pump is adapted to be connected to the inlet; the bearing is adapted to be connected to the outlet. The membrane is disposed in the chamber. The restricting plane is an inner surface of the casing adjacent to the outlet and towards the membrane. Dimensionless stiffness of the membrane is Kr*, and 1.33&#x2264;K*&#x2264;2. K*=KL/(pA). Here, Kis stiffness of the membrane, Lis a distance from the membrane to the restricting plane when no fluid is supplied by the pump (i.e., assembling clearance of the membrane), pis pressure supplied by the pump, and Ais an effective area of the restricting plane. A hydrostatic bearing module having the membrane restrictor is further provided.

Membrane restrictor and hydrostatic bearing module

A MEMS device includes: a substrate; a proof mass suspended over the substrate, the proof mass including at least one proof mass body and a proof mass frame connected to and accommodating the proof mass body, the proof mass frame including at least one self-test frame; and at least one self-test electrode inside the self-test frame, and connected to the substrate; wherein when a voltage difference is applied between the self-test electrode and the self-test frame, the proof mass is driven to have an in-plane movement, and wherein the self-test electrode and the self-test frame do not form a sensing capacitor in between.

Micro-electro-mechanical system device

The invention provides a MEMS device. The MEMS device includes: a substrate; a proof mass, including at least two slots, each of the slots including an inner space and an opening, the inner space being relatively closer to a center area of the proof mass than the opening; at least two anchors located in the corresponding slots and connected to the substrate; at least two linkages located in the corresponding slots and connected to the corresponding anchors; and a multi-dimensional spring structure for assisting a multi-dimensional movement of the proof mass, the multi-dimensional spring structure surrounding a periphery of the proof mass, and connected to the substrate through the linkages and the anchors. The multi-dimensional spring structure includes first and second springs for assisting an out-of-plane movement and an in-plane movement of the proof mass.

Micro-electro-mechanical system (MEMS) device with multi-dimensional spring structure and frame

The present invention discloses a MEMS device. The MEMS device includes a substrate, a proof mass, a frame spring and an anchor. The proof mass is connected to the substrate through the frame spring and the anchor. The proof mass includes a proof mass body, a proof mass frame surrounding the proof mass body, a linking element connecting the proof mass body to the proof mass frame, and a stopper between the proof mass body and the proof mass frame in a displacement direction to limit the displacement of the proof mass body. The stopper is connected to the proof mass frame as a part of the proof mass and contributes to the mass quantity of the proof mass.

Micro-electro-mechanical system (MEMS) device

An antenna structure includes a main portion, a first radiating portion connected to the main portion, a second radiating portion connected to the main portion and opposite to the first radiating portion, and a coupling portion spaced from and coplanar with the main portion and opposite to the second radiating portion. The main portion and the first radiating portion excite a low frequency mode, the main portion, the first radiating portion, the second radiating portion, and the coupling portion excite a high frequency mode, and when the antenna structure is interfered by a user's human body when close to the user's human body, the coupling portion transmits the interference to ground. A wireless communication device employing the antenna structure is also disclosed.

Growing community of inventors

Taoyuan, Taiwan

Shih-Chieh Lin